Zephyr Project API  3.3.0
A Scalable Open Source RTOS
ccc.h File Reference
#include <zephyr/types.h>
#include <zephyr/device.h>
#include <zephyr/toolchain.h>
#include <zephyr/sys/util.h>

Go to the source code of this file.

Data Structures

struct  i3c_ccc_target_payload
 Payload structure for Direct CCC to one target. More...
 
struct  i3c_ccc_payload
 Payload structure for one CCC transaction. More...
 
struct  i3c_ccc_events
 Payload for ENEC/DISEC CCC (Target Events Command). More...
 
struct  i3c_ccc_mwl
 Payload for SETMWL/GETMWL CCC (Set/Get Maximum Write Length). More...
 
struct  i3c_ccc_mrl
 Payload for SETMRL/GETMRL CCC (Set/Get Maximum Read Length). More...
 
struct  i3c_ccc_deftgts_active_controller
 The active controller part of payload for DEFTGTS CCC. More...
 
struct  i3c_ccc_deftgts_target
 The target device part of payload for DEFTGTS CCC. More...
 
struct  i3c_ccc_deftgts
 Payload for DEFTGTS CCC (Define List of Targets). More...
 
struct  i3c_ccc_address
 Payload for a single device address. More...
 
struct  i3c_ccc_getpid
 Payload for GETPID CCC (Get Provisioned ID). More...
 
struct  i3c_ccc_getbcr
 Payload for GETBCR CCC (Get Bus Characteristics Register). More...
 
struct  i3c_ccc_getdcr
 Payload for GETDCR CCC (Get Device Characteristics Register). More...
 
union  i3c_ccc_getstatus
 Payload for GETSTATUS CCC (Get Device Status). More...
 
struct  i3c_ccc_setbrgtgt_tgt
 One Bridged Target for SETBRGTGT payload. More...
 
struct  i3c_ccc_setbrgtgt
 Payload for SETBRGTGT CCC (Set Bridge Targets). More...
 
union  i3c_ccc_getmxds
 Payload for GETMXDS CCC (Get Max Data Speed). More...
 
struct  i3c_ccc_getcaps
 Payload for GETCAPS CCC (Get Optional Feature Capabilities). More...
 

Macros

#define I3C_CCC_BROADCAST_MAX_ID   0x7FU
 
#define I3C_CCC_ENEC(broadcast)   ((broadcast) ? 0x00U : 0x80U)
 
#define I3C_CCC_DISEC(broadcast)   ((broadcast) ? 0x01U : 0x81U)
 
#define I3C_CCC_ENTAS(as, broadcast)   (((broadcast) ? 0x02U : 0x82U) + (as))
 
#define I3C_CCC_ENTAS0(broadcast)   I3C_CCC_ENTAS(0, broadcast)
 
#define I3C_CCC_ENTAS1(broadcast)   I3C_CCC_ENTAS(1, broadcast)
 
#define I3C_CCC_ENTAS2(broadcast)   I3C_CCC_ENTAS(2, broadcast)
 
#define I3C_CCC_ENTAS3(broadcast)   I3C_CCC_ENTAS(3, broadcast)
 
#define I3C_CCC_RSTDAA   0x06U
 
#define I3C_CCC_ENTDAA   0x07U
 
#define I3C_CCC_DEFTGTS   0x08U
 
#define I3C_CCC_SETMWL(broadcast)   ((broadcast) ? 0x09U : 0x89U)
 
#define I3C_CCC_SETMRL(broadcast)   ((broadcast) ? 0x0AU : 0x8AU)
 
#define I3C_CCC_ENTTM   0x0BU
 
#define I3C_CCC_SETBUSCON   0x0CU
 
#define I3C_CCC_ENDXFER(broadcast)   ((broadcast) ? 0x12U : 0x92U)
 
#define I3C_CCC_ENTHDR(x)   (0x20U + (x))
 
#define I3C_CCC_ENTHDR0   0x20U
 
#define I3C_CCC_ENTHDR1   0x21U
 
#define I3C_CCC_ENTHDR2   0x22U
 
#define I3C_CCC_ENTHDR3   0x23U
 
#define I3C_CCC_ENTHDR4   0x24U
 
#define I3C_CCC_ENTHDR5   0x25U
 
#define I3C_CCC_ENTHDR6   0x26U
 
#define I3C_CCC_ENTHDR7   0x27U
 
#define I3C_CCC_SETXTIME(broadcast)   ((broadcast) ? 0x28U : 0x98U)
 
#define I3C_CCC_SETAASA   0x29U
 
#define I3C_CCC_RSTACT(broadcast)   ((broadcast) ? 0x2AU : 0x9AU)
 
#define I3C_CCC_DEFGRPA   0x2BU
 
#define I3C_CCC_RSTGRPA(broadcast)   ((broadcast) ? 0x2CU : 0x9CU)
 
#define I3C_CCC_MLANE(broadcast)   ((broadcast) ? 0x2DU : 0x9DU)
 
#define I3C_CCC_VENDOR(broadcast, id)   ((id) + ((broadcast) ? 0x61U : 0xE0U))
 
#define I3C_CCC_SETDASA   0x87U
 
#define I3C_CCC_SETNEWDA   0x88U
 
#define I3C_CCC_GETMWL   0x8BU
 
#define I3C_CCC_GETMRL   0x8CU
 
#define I3C_CCC_GETPID   0x8DU
 
#define I3C_CCC_GETBCR   0x8EU
 
#define I3C_CCC_GETDCR   0x8FU
 
#define I3C_CCC_GETSTATUS   0x90U
 
#define I3C_CCC_GETACCCR   0x91U
 
#define I3C_CCC_SETBRGTGT   0x93U
 
#define I3C_CCC_GETMXDS   0x94U
 
#define I3C_CCC_GETCAPS   0x95U
 
#define I3C_CCC_SETROUTE   0x96U
 
#define I3C_CCC_D2DXFER   0x97U
 
#define I3C_CCC_GETXTIME   0x99U
 
#define I3C_CCC_SETGRPA   0x9BU
 
#define I3C_CCC_ENEC_EVT_ENINTR   BIT(0)
 
#define I3C_CCC_ENEC_EVT_ENCR   BIT(1)
 
#define I3C_CCC_ENEC_EVT_ENHJ   BIT(3)
 
#define I3C_CCC_ENEC_EVT_ALL    (I3C_CCC_ENEC_EVT_ENINTR | I3C_CCC_ENEC_EVT_ENCR | I3C_CCC_ENEC_EVT_ENHJ)
 
#define I3C_CCC_DISEC_EVT_DISINTR   BIT(0)
 
#define I3C_CCC_DISEC_EVT_DISCR   BIT(1)
 
#define I3C_CCC_DISEC_EVT_DISHJ   BIT(3)
 
#define I3C_CCC_DISEC_EVT_ALL    (I3C_CCC_DISEC_EVT_DISINTR | I3C_CCC_DISEC_EVT_DISCR | I3C_CCC_DISEC_EVT_DISHJ)
 
#define I3C_CCC_EVT_INTR   BIT(0)
 
#define I3C_CCC_EVT_CR   BIT(1)
 
#define I3C_CCC_EVT_HJ   BIT(3)
 
#define I3C_CCC_EVT_ALL    (I3C_CCC_EVT_INTR | I3C_CCC_EVT_CR | I3C_CCC_EVT_HJ)
 
#define I3C_CCC_GETSTATUS_PROTOCOL_ERR   BIT(5)
 
#define I3C_CCC_GETSTATUS_ACTIVITY_MODE_SHIFT   6
 
#define I3C_CCC_GETSTATUS_ACTIVITY_MODE_MASK    (0x03U << I3C_CCC_GETSTATUS_ACTIVITY_MODE_SHIFT)
 
#define I3C_CCC_GETSTATUS_ACTIVITY_MODE(status)
 
#define I3C_CCC_GETSTATUS_NUM_INT_SHIFT   0
 
#define I3C_CCC_GETSTATUS_NUM_INT_MASK    (0x0FU << I3C_CCC_GETSTATUS_NUM_INT_SHIFT)
 
#define I3C_CCC_GETSTATUS_NUM_INT(status)
 
#define I3C_CCC_GETSTATUS_PRECR_DEEP_SLEEP_DETECTED   BIT(0)
 
#define I3C_CCC_GETSTATUS_PRECR_HANDOFF_DELAY_NACK   BIT(1)
 
#define I3C_CCC_GETMXDS_MAX_SDR_FSCL_MAX   0
 
#define I3C_CCC_GETMXDS_MAX_SDR_FSCL_8MHZ   1
 
#define I3C_CCC_GETMXDS_MAX_SDR_FSCL_6MHZ   2
 
#define I3C_CCC_GETMXDS_MAX_SDR_FSCL_4MHZ   3
 
#define I3C_CCC_GETMXDS_MAX_SDR_FSCL_2MHZ   4
 
#define I3C_CCC_GETMXDS_TSCO_8NS   0
 
#define I3C_CCC_GETMXDS_TSCO_9NS   1
 
#define I3C_CCC_GETMXDS_TSCO_10NS   2
 
#define I3C_CCC_GETMXDS_TSCO_11NS   3
 
#define I3C_CCC_GETMXDS_TSCO_12NS   4
 
#define I3C_CCC_GETMXDS_TSCO_GT_12NS   7
 
#define I3C_CCC_GETMXDS_MAXWR_DEFINING_BYTE_SUPPORT   BIT(3)
 
#define I3C_CCC_GETMXDS_MAXWR_MAX_SDR_FSCL_SHIFT   0
 
#define I3C_CCC_GETMXDS_MAXWR_MAX_SDR_FSCL_MASK    (0x07U << I3C_CCC_GET_MXDS_MAXWR_MAX_SDR_FSCL_SHIFT)
 
#define I3C_CCC_GETMXDS_MAXWR_MAX_SDR_FSCL(maxwr)
 
#define I3C_CCC_GETMXDS_MAXRD_W2R_PERMITS_STOP_BETWEEN   BIT(6)
 
#define I3C_CCC_GETMXDS_MAXRD_TSCO_SHIFT   3
 
#define I3C_CCC_GETMXDS_MAXRD_TSCO_MASK    (0x07U << I3C_CCC_GETMXDS_MAXRD_TSCO_SHIFT)
 
#define I3C_CCC_GETMXDS_MAXRD_TSCO(maxrd)
 
#define I3C_CCC_GETMXDS_MAXRD_MAX_SDR_FSCL_SHIFT   0
 
#define I3C_CCC_GETMXDS_MAXRD_MAX_SDR_FSCL_MASK    (0x07U << I3C_CCC_GET_MXDS_MAXRD_MAX_SDR_FSCL_SHIFT)
 
#define I3C_CCC_GETMXDS_MAXRD_MAX_SDR_FSCL(maxrd)
 
#define I3C_CCC_GETMXDS_CRDHLY1_SET_BUS_ACT_STATE   BIT(2)
 
#define I3C_CCC_GETMXDS_CRDHLY1_CTRL_HANDOFF_ACT_STATE_SHIFT   0
 
#define I3C_CCC_GETMXDS_CRDHLY1_CTRL_HANDOFF_ACT_STATE_MASK    (0x03U << I3C_CCC_GETMXDS_CRDHLY1_SET_BUS_ACT_STATE_SHIFT)
 
#define I3C_CCC_GETMXDS_CRDHLY1_CTRL_HANDOFF_ACT_STATE(crhdly1)
 
#define I3C_CCC_GETCAPS1_HDR_DDR   BIT(0)
 
#define I3C_CCC_GETCAPS1_HDR_BT   BIT(3)
 
#define I3C_CCC_GETCAPS1_HDR_MODE(x)   BIT(x)
 
#define I3C_CCC_GETCAPS1_HDR_MODE0   BIT(0)
 
#define I3C_CCC_GETCAPS1_HDR_MODE1   BIT(1)
 
#define I3C_CCC_GETCAPS1_HDR_MODE2   BIT(2)
 
#define I3C_CCC_GETCAPS1_HDR_MODE3   BIT(3)
 
#define I3C_CCC_GETCAPS1_HDR_MODE4   BIT(4)
 
#define I3C_CCC_GETCAPS1_HDR_MODE5   BIT(5)
 
#define I3C_CCC_GETCAPS1_HDR_MODE6   BIT(6)
 
#define I3C_CCC_GETCAPS1_HDR_MODE7   BIT(7)
 
#define I3C_CCC_GETCAPS2_HDRDDR_WRITE_ABORT   BIT(6)
 
#define I3C_CCC_GETCAPS2_HDRDDR_ABORT_CRC   BIT(7)
 
#define I3C_CCC_GETCAPS2_GRPADDR_CAP_SHIFT   4
 
#define I3C_CCC_GETCAPS2_GRPADDR_CAP_MASK    (0x03U << I3C_CCC_GETCAPS2_GRPADDR_CAP_SHIFT)
 
#define I3C_CCC_GETCAPS2_GRPADDR_CAP(getcaps2)
 
#define I3C_CCC_GETCAPS2_SPEC_VER_SHIFT   0
 
#define I3C_CCC_GETCAPS2_SPEC_VER_MASK    (0x0FU << I3C_CCC_GETCAPS2_SPEC_VER_SHIFT)
 
#define I3C_CCC_GETCAPS2_SPEC_VER(getcaps2)
 
#define I3C_CCC_GETCAPS3_MLAME_SUPPORT   BIT(0)
 
#define I3C_CCC_GETCAPS3_D2DXFER_SUPPORT   BIT(1)
 
#define I3C_CCC_GETCAPS3_D3DXFER_IBI_CAPABLE   BIT(2)
 
#define I3C_CCC_GETCAPS3_GETCAPS_DEFINING_BYTE_SUPPORT   BIT(3)
 
#define I3C_CCC_GETCAPS3_GETSTATUS_DEFINING_BYTE_SUPPORT   BIT(4)
 
#define I3C_CCC_GETCAPS3_HDRBT_CRC32_SUPPORT   BIT(5)
 
#define I3C_CCC_GETCAPS3_IBI_MDR_PENDING_READ_NOTIFICATION   BIT(6)
 

Enumerations

enum  i3c_ccc_getstatus_fmt { GETSTATUS_FORMAT_1 , GETSTATUS_FORMAT_2 }
 Indicate which format of GETSTATUS to use. More...
 
enum  i3c_ccc_getstatus_defbyte { GETSTATUS_FORMAT_2_TGTSTAT = 0x00U , GETSTATUS_FORMAT_2_PRECR = 0x91U , GETSTATUS_FORMAT_2_INVALID = 0x100U }
 
enum  i3c_ccc_rstact_defining_byte {
  I3C_CCC_RSTACT_NO_RESET = 0x00U , I3C_CCC_RSTACT_PERIPHERAL_ONLY = 0x01U , I3C_CCC_RSTACT_RESET_WHOLE_TARGET = 0x02U , I3C_CCC_RSTACT_DEBUG_NETWORK_ADAPTER = 0x03U ,
  I3C_CCC_RSTACT_VIRTUAL_TARGET_DETECT = 0x04U
}
 

Functions

static bool i3c_ccc_is_payload_broadcast (const struct i3c_ccc_payload *payload)
 Test if I3C CCC payload is for broadcast. More...
 
int i3c_ccc_do_getbcr (struct i3c_device_desc *target, struct i3c_ccc_getbcr *bcr)
 Get BCR from a target. More...
 
int i3c_ccc_do_getdcr (struct i3c_device_desc *target, struct i3c_ccc_getdcr *dcr)
 Get DCR from a target. More...
 
int i3c_ccc_do_getpid (struct i3c_device_desc *target, struct i3c_ccc_getpid *pid)
 Get PID from a target. More...
 
int i3c_ccc_do_rstact_all (const struct device *controller, enum i3c_ccc_rstact_defining_byte action)
 Broadcast RSTACT to reset I3C Peripheral. More...
 
int i3c_ccc_do_rstdaa_all (const struct device *controller)
 Broadcast RSTDAA to reset dynamic addresses for all targets. More...
 
int i3c_ccc_do_setdasa (const struct i3c_device_desc *target)
 Set Dynamic Address from Static Address for a target. More...
 
int i3c_ccc_do_events_all_set (const struct device *controller, bool enable, struct i3c_ccc_events *events)
 Broadcast ENEC/DISEC to enable/disable target events. More...
 
int i3c_ccc_do_events_set (struct i3c_device_desc *target, bool enable, struct i3c_ccc_events *events)
 Direct CCC ENEC/DISEC to enable/disable target events. More...
 
int i3c_ccc_do_setmwl_all (const struct device *controller, const struct i3c_ccc_mwl *mwl)
 Broadcast SETMWL to Set Maximum Write Length. More...
 
int i3c_ccc_do_setmwl (const struct i3c_device_desc *target, const struct i3c_ccc_mwl *mwl)
 Single target SETMWL to Set Maximum Write Length. More...
 
int i3c_ccc_do_getmwl (const struct i3c_device_desc *target, struct i3c_ccc_mwl *mwl)
 Single target GETMWL to Get Maximum Write Length. More...
 
int i3c_ccc_do_setmrl_all (const struct device *controller, const struct i3c_ccc_mrl *mrl, bool has_ibi_size)
 Broadcast SETMRL to Set Maximum Read Length. More...
 
int i3c_ccc_do_setmrl (const struct i3c_device_desc *target, const struct i3c_ccc_mrl *mrl)
 Single target SETMRL to Set Maximum Read Length. More...
 
int i3c_ccc_do_getmrl (const struct i3c_device_desc *target, struct i3c_ccc_mrl *mrl)
 Single target GETMRL to Get Maximum Read Length. More...
 
int i3c_ccc_do_getstatus (const struct i3c_device_desc *target, union i3c_ccc_getstatus *status, enum i3c_ccc_getstatus_fmt fmt, enum i3c_ccc_getstatus_defbyte defbyte)
 Single target GETSTATUS to Get Target Status. More...
 
static int i3c_ccc_do_getstatus_fmt1 (const struct i3c_device_desc *target, union i3c_ccc_getstatus *status)
 Single target GETSTATUS to Get Target Status (Format 1). More...
 
static int i3c_ccc_do_getstatus_fmt2 (const struct i3c_device_desc *target, union i3c_ccc_getstatus *status, enum i3c_ccc_getstatus_defbyte defbyte)
 Single target GETSTATUS to Get Target Status (Format 2). More...