gic.h File Reference

Driver for ARM Generic Interrupt Controller. More...

#include <zephyr/types.h>
#include <zephyr/device.h>

Go to the source code of this file.

Macros
#define	GIC_DIST_BASE   DT_REG_ADDR_BY_IDX(DT_INST(0, arm_gic), 0)
#define	GIC_CPU_BASE   DT_REG_ADDR_BY_IDX(DT_INST(0, arm_gic), 1)
#define	GICD_CTLR   (GIC_DIST_BASE + 0x0)
#define	GICD_TYPER   (GIC_DIST_BASE + 0x4)
#define	GICD_IIDR   (GIC_DIST_BASE + 0x8)
#define	GICD_IGROUPRn   (GIC_DIST_BASE + 0x80)
#define	GICD_ISENABLERn   (GIC_DIST_BASE + 0x100)
#define	GICD_ICENABLERn   (GIC_DIST_BASE + 0x180)
#define	GICD_ISPENDRn   (GIC_DIST_BASE + 0x200)
#define	GICD_ICPENDRn   (GIC_DIST_BASE + 0x280)
#define	GICD_ISACTIVERn   (GIC_DIST_BASE + 0x300)
#define	GICD_IPRIORITYRn   (GIC_DIST_BASE + 0x400)
#define	GICD_ITARGETSRn   (GIC_DIST_BASE + 0x800)
#define	GICD_ICFGRn   (GIC_DIST_BASE + 0xc00)
#define	GICD_SGIR   (GIC_DIST_BASE + 0xf00)
#define	GICC_CTLR   (GIC_CPU_BASE + 0x0)
#define	GICC_PMR   (GIC_CPU_BASE + 0x4)
#define	GICC_BPR   (GIC_CPU_BASE + 0x8)
#define	GICC_IAR   (GIC_CPU_BASE + 0xc)
#define	GICC_EOIR   (GIC_CPU_BASE + 0x10)
#define	GICC_CTLR_ENABLEGRP0   BIT(0)
#define	GICC_CTLR_ENABLEGRP1   BIT(1)
#define	GICC_CTLR_ENABLE_MASK   (GICC_CTLR_ENABLEGRP0 | GICC_CTLR_ENABLEGRP1)
#define	GICD_SGIR_TGTFILT(x)   ((x) << 24)
#define	GICD_SGIR_TGTFILT_CPULIST   GICD_SGIR_TGTFILT(0b00)
#define	GICD_SGIR_TGTFILT_ALLBUTREQ   GICD_SGIR_TGTFILT(0b01)
#define	GICD_SGIR_TGTFILT_REQONLY   GICD_SGIR_TGTFILT(0b10)
#define	GICD_SGIR_CPULIST(x)   ((x) << 16)
#define	GICD_SGIR_CPULIST_CPU(n)   GICD_SGIR_CPULIST(BIT(n))
#define	GICD_SGIR_CPULIST_MASK   0xff
#define	GICD_SGIR_NSATT   BIT(15)
#define	GICD_SGIR_SGIINTID(x)   (x)
#define	GICD_ICFGR_MASK   BIT_MASK(2)
#define	GICD_ICFGR_TYPE   BIT(1)
#define	GICD_TYPER_ITLINESNUM_MASK   0x1f
#define	GICD_TYPER_IDBITS(typer)   ((((typer) >> 19) & 0x1f) + 1)
#define	GIC_SGI_INT_BASE   0
#define	GIC_PPI_INT_BASE   16
#define	GIC_IS_SGI(intid)
#define	GIC_SPI_INT_BASE   32
#define	GIC_SPI_MAX_INTID   1019
#define	GIC_IS_SPI(intid)
#define	GIC_NUM_INTR_PER_REG   32
#define	GIC_NUM_CFG_PER_REG   16
#define	GIC_NUM_PRI_PER_REG   4
#define	GIC_IDLE_PRIO   0xff
#define	GIC_PRI_MASK   0xff
#define	GIC_INT_DEF_PRI_X4   0xa0a0a0a0
#define	GIC_INTID_SPURIOUS   1023
#define	GIC_NUM_CPU_IF   CONFIG_MP_MAX_NUM_CPUS

Functions
void	arm_gic_irq_enable (unsigned int irq)
	Enable interrupt. More...
void	arm_gic_irq_disable (unsigned int irq)
	Disable interrupt. More...
bool	arm_gic_irq_is_enabled (unsigned int irq)
	Check if an interrupt is enabled. More...
void	arm_gic_irq_set_priority (unsigned int irq, unsigned int prio, unsigned int flags)
	Set interrupt priority. More...
unsigned int	arm_gic_get_active (void)
	Get active interrupt ID. More...
void	arm_gic_eoi (unsigned int irq)
	Signal end-of-interrupt. More...
void	arm_gic_secondary_init (void)
	Initialize GIC of secondary cores. More...
void	gic_raise_sgi (unsigned int sgi_id, uint64_t target_aff, uint16_t target_list)
	raise SGI to target cores More...

Detailed Description

Driver for ARM Generic Interrupt Controller.

The Generic Interrupt Controller (GIC) is the default interrupt controller for the ARM A and R profile cores. This driver is used by the ARM arch implementation to handle interrupts.

Macro Definition Documentation

GIC_CPU_BASE

#define GIC_CPU_BASE   DT_REG_ADDR_BY_IDX(DT_INST(0, arm_gic), 1)

GIC_DIST_BASE

#define GIC_DIST_BASE   DT_REG_ADDR_BY_IDX(DT_INST(0, arm_gic), 0)

GIC_IDLE_PRIO

#define GIC_IDLE_PRIO   0xff

GIC_INT_DEF_PRI_X4

#define GIC_INT_DEF_PRI_X4   0xa0a0a0a0

GIC_INTID_SPURIOUS

#define GIC_INTID_SPURIOUS   1023

GIC_IS_SGI

#define GIC_IS_SGI

(

intid

)

Value:

                                         (((intid) >= GIC_SGI_INT_BASE) && \
                                         ((intid) < GIC_PPI_INT_BASE))

GIC_IS_SPI

#define GIC_IS_SPI

(

intid

)

Value:

                                        (((intid) >= GIC_SPI_INT_BASE) && \
                                        ((intid) <= GIC_SPI_MAX_INTID))

GIC_NUM_CFG_PER_REG

#define GIC_NUM_CFG_PER_REG   16

GIC_NUM_CPU_IF

#define GIC_NUM_CPU_IF   CONFIG_MP_MAX_NUM_CPUS

GIC_NUM_INTR_PER_REG

#define GIC_NUM_INTR_PER_REG   32

GIC_NUM_PRI_PER_REG

#define GIC_NUM_PRI_PER_REG   4

GIC_PPI_INT_BASE

#define GIC_PPI_INT_BASE   16

GIC_PRI_MASK

#define GIC_PRI_MASK   0xff

GIC_SGI_INT_BASE

#define GIC_SGI_INT_BASE   0

GIC_SPI_INT_BASE

#define GIC_SPI_INT_BASE   32

GIC_SPI_MAX_INTID

#define GIC_SPI_MAX_INTID   1019

GICC_BPR

#define GICC_BPR   (GIC_CPU_BASE + 0x8)

GICC_CTLR

#define GICC_CTLR   (GIC_CPU_BASE + 0x0)

GICC_CTLR_ENABLE_MASK

#define GICC_CTLR_ENABLE_MASK   (GICC_CTLR_ENABLEGRP0 | GICC_CTLR_ENABLEGRP1)

GICC_CTLR_ENABLEGRP0

#define GICC_CTLR_ENABLEGRP0   BIT(0)

GICC_CTLR_ENABLEGRP1

#define GICC_CTLR_ENABLEGRP1   BIT(1)

GICC_EOIR

#define GICC_EOIR   (GIC_CPU_BASE + 0x10)

GICC_IAR

#define GICC_IAR   (GIC_CPU_BASE + 0xc)

GICC_PMR

#define GICC_PMR   (GIC_CPU_BASE + 0x4)

GICD_CTLR

#define GICD_CTLR   (GIC_DIST_BASE + 0x0)

GICD_ICENABLERn

#define GICD_ICENABLERn   (GIC_DIST_BASE + 0x180)

GICD_ICFGR_MASK

#define GICD_ICFGR_MASK   BIT_MASK(2)

GICD_ICFGR_TYPE

#define GICD_ICFGR_TYPE   BIT(1)

GICD_ICFGRn

#define GICD_ICFGRn   (GIC_DIST_BASE + 0xc00)

GICD_ICPENDRn

#define GICD_ICPENDRn   (GIC_DIST_BASE + 0x280)

GICD_IGROUPRn

#define GICD_IGROUPRn   (GIC_DIST_BASE + 0x80)

GICD_IIDR

#define GICD_IIDR   (GIC_DIST_BASE + 0x8)

GICD_IPRIORITYRn

#define GICD_IPRIORITYRn   (GIC_DIST_BASE + 0x400)

GICD_ISACTIVERn

#define GICD_ISACTIVERn   (GIC_DIST_BASE + 0x300)

GICD_ISENABLERn

#define GICD_ISENABLERn   (GIC_DIST_BASE + 0x100)

GICD_ISPENDRn

#define GICD_ISPENDRn   (GIC_DIST_BASE + 0x200)

GICD_ITARGETSRn

#define GICD_ITARGETSRn   (GIC_DIST_BASE + 0x800)

GICD_SGIR

#define GICD_SGIR   (GIC_DIST_BASE + 0xf00)

GICD_SGIR_CPULIST

#define GICD_SGIR_CPULIST

(

x

)

((x) << 16)

GICD_SGIR_CPULIST_CPU

#define GICD_SGIR_CPULIST_CPU

(

n

)

GICD_SGIR_CPULIST(BIT(n))

GICD_SGIR_CPULIST_MASK

#define GICD_SGIR_CPULIST_MASK   0xff

GICD_SGIR_NSATT

#define GICD_SGIR_NSATT   BIT(15)

GICD_SGIR_SGIINTID

#define GICD_SGIR_SGIINTID

(

x

)

(x)

GICD_SGIR_TGTFILT

#define GICD_SGIR_TGTFILT

(

x

)

((x) << 24)

GICD_SGIR_TGTFILT_ALLBUTREQ

#define GICD_SGIR_TGTFILT_ALLBUTREQ   GICD_SGIR_TGTFILT(0b01)

GICD_SGIR_TGTFILT_CPULIST

#define GICD_SGIR_TGTFILT_CPULIST   GICD_SGIR_TGTFILT(0b00)

GICD_SGIR_TGTFILT_REQONLY

#define GICD_SGIR_TGTFILT_REQONLY   GICD_SGIR_TGTFILT(0b10)

GICD_TYPER

#define GICD_TYPER   (GIC_DIST_BASE + 0x4)

GICD_TYPER_IDBITS

#define GICD_TYPER_IDBITS

(

typer

)

((((typer) >> 19) & 0x1f) + 1)

GICD_TYPER_ITLINESNUM_MASK

#define GICD_TYPER_ITLINESNUM_MASK   0x1f

Function Documentation

arm_gic_eoi()

void arm_gic_eoi

(

unsigned int

irq

)

Signal end-of-interrupt.

Parameters

irq	interrupt ID

arm_gic_get_active()

unsigned int arm_gic_get_active

(

void

)

Get active interrupt ID.

Returns

Returns the ID of an active interrupt

arm_gic_irq_disable()

void arm_gic_irq_disable

(

unsigned int

irq

)

Disable interrupt.

Parameters

irq	interrupt ID

arm_gic_irq_enable()

void arm_gic_irq_enable

(

unsigned int

irq

)

Enable interrupt.

Parameters

irq	interrupt ID

arm_gic_irq_is_enabled()

bool arm_gic_irq_is_enabled

(

unsigned int

irq

)

Check if an interrupt is enabled.

Parameters

irq	interrupt ID

Returns

Returns true if interrupt is enabled, false otherwise

arm_gic_irq_set_priority()

void arm_gic_irq_set_priority	(	unsigned int	irq,
		unsigned int	prio,
		unsigned int	flags
	)

Set interrupt priority.

Parameters

irq	interrupt ID
prio	interrupt priority
flags	interrupt flags

arm_gic_secondary_init()

void arm_gic_secondary_init

(

void

)

Initialize GIC of secondary cores.

gic_raise_sgi()

void gic_raise_sgi	(	unsigned int	sgi_id,
		uint64_t	target_aff,
		uint16_t	target_list
	)

raise SGI to target cores

Parameters

sgi_id	SGI ID 0 to 15
target_aff	target affinity in mpidr form. Aff level 1 2 3 will be extracted by api.
target_list	bitmask of target cores