pinctrl_soc_gd32_common.h File Reference

#include <zephyr/devicetree.h>
#include <zephyr/types.h>
#include <dt-bindings/pinctrl/gd32-afio.h>

Go to the source code of this file.

Macros
#define	GD32_PUPD_GET(pincfg)    (((pincfg) >> GD32_PUPD_POS) & GD32_PUPD_MSK)
#define	GD32_OTYPE_GET(pincfg)    (((pincfg) >> GD32_OTYPE_POS) & GD32_OTYPE_MSK)
#define	GD32_OSPEED_GET(pincfg)    (((pincfg) >> GD32_OSPEED_POS) & GD32_OSPEED_MSK)
GD32 PUPD (values match the ones in the HAL for AF model).
#define	GD32_PUPD_NONE   0U
#define	GD32_PUPD_PULLUP   1U
#define	GD32_PUPD_PULLDOWN   2U
GD32 OTYPE (values match the ones in the HAL for AF model).
#define	GD32_OTYPE_PP   0U
#define	GD32_OTYPE_OD   1U
GD32 OSPEED (values match the ones in the HAL for AF model, mode minus
one for AFIO model).
#define	GD32_OSPEED_10MHZ   0U
#define	GD32_OSPEED_2MHZ   1U
#define	GD32_OSPEED_50MHZ   2U
#define	GD32_OSPEED_MAX   3U
GD32 pin configuration bit field mask and positions.
Fields: 31..29: Pull-up/down 28: Output type 27..26: Output speed
#define	GD32_PUPD_MSK   0x3U
#define	GD32_PUPD_POS   29U
#define	GD32_OTYPE_MSK   0x1U
#define	GD32_OTYPE_POS   28U
#define	GD32_OSPEED_MSK   0x3U
#define	GD32_OSPEED_POS   26U

Detailed Description

Gigadevice SoC specific helpers for pinctrl driver

Macro Definition Documentation

GD32_OSPEED_10MHZ

#define GD32_OSPEED_10MHZ   0U

Maximum 10MHz

GD32_OSPEED_2MHZ

#define GD32_OSPEED_2MHZ   1U

Maximum 2MHz

GD32_OSPEED_50MHZ

#define GD32_OSPEED_50MHZ   2U

Maximum 50MHz

GD32_OSPEED_GET

#define GD32_OSPEED_GET

(

pincfg

)

(((pincfg) >> GD32_OSPEED_POS) & GD32_OSPEED_MSK)

Obtain OSPEED field from pinctrl_soc_pin_t configuration.

Parameters

pincfg

pinctrl_soc_pin_t bit field value.

GD32_OSPEED_MAX

#define GD32_OSPEED_MAX   3U

Maximum speed

GD32_OSPEED_MSK

#define GD32_OSPEED_MSK   0x3U

OSPEED field mask.

GD32_OSPEED_POS

#define GD32_OSPEED_POS   26U

OSPEED field position.

GD32_OTYPE_GET

#define GD32_OTYPE_GET

(

pincfg

)

(((pincfg) >> GD32_OTYPE_POS) & GD32_OTYPE_MSK)

Obtain OTYPE field from pinctrl_soc_pin_t configuration.

Parameters

pincfg

pinctrl_soc_pin_t bit field value.

GD32_OTYPE_MSK

#define GD32_OTYPE_MSK   0x1U

OTYPE field mask.

GD32_OTYPE_OD

#define GD32_OTYPE_OD   1U

Open-drain

GD32_OTYPE_POS

#define GD32_OTYPE_POS   28U

OTYPE field position.

GD32_OTYPE_PP

#define GD32_OTYPE_PP   0U

Push-pull

GD32_PUPD_GET

#define GD32_PUPD_GET

(

pincfg

)

(((pincfg) >> GD32_PUPD_POS) & GD32_PUPD_MSK)

Obtain PUPD field from pinctrl_soc_pin_t configuration.

Parameters

pincfg

pinctrl_soc_pin_t bit field value.

GD32_PUPD_MSK

#define GD32_PUPD_MSK   0x3U

PUPD field mask.

GD32_PUPD_NONE

#define GD32_PUPD_NONE   0U

No pull-up/down

GD32_PUPD_POS

#define GD32_PUPD_POS   29U

PUPD field position.

GD32_PUPD_PULLDOWN

#define GD32_PUPD_PULLDOWN   2U

Pull-down

GD32_PUPD_PULLUP

#define GD32_PUPD_PULLUP   1U

Pull-up