stm32f4_clock.h File Reference

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Macros
#define	STM32_CLOCK_BUS_AHB1   0x030
#define	STM32_CLOCK_BUS_AHB2   0x034
#define	STM32_CLOCK_BUS_AHB3   0x038
#define	STM32_CLOCK_BUS_APB1   0x040
#define	STM32_CLOCK_BUS_APB2   0x044
#define	STM32_CLOCK_BUS_APB3   0x0A8
#define	STM32_PERIPH_BUS_MIN   STM32_CLOCK_BUS_AHB1
#define	STM32_PERIPH_BUS_MAX   STM32_CLOCK_BUS_APB3
#define	STM32_SRC_PLL_P   0x001
#define	STM32_SRC_PLL_Q   0x002
#define	STM32_SRC_PLL_R   0x003
#define	STM32_SRC_LSE   0x004
#define	STM32_SRC_LSI   0x005
#define	STM32_SRC_SYSCLK   0x006
#define	STM32_CLOCK_REG_MASK   0xFFU
	STM32 clock configuration bit field. More...
#define	STM32_CLOCK_REG_SHIFT   0U
#define	STM32_CLOCK_SHIFT_MASK   0x1FU
#define	STM32_CLOCK_SHIFT_SHIFT   8U
#define	STM32_CLOCK_MASK_MASK   0x7U
#define	STM32_CLOCK_MASK_SHIFT   13U
#define	STM32_CLOCK_VAL_MASK   0x7U
#define	STM32_CLOCK_VAL_SHIFT   16U
#define	STM32_CLOCK(val, mask, shift, reg)
#define	BDCR_REG   0x70
	RCC_BDCR register offset. More...
#define	RTC_SEL(val)   STM32_CLOCK(val, 3, 8, BDCR_REG)
	Device domain clocks selection helpers. More...
#define	NO_SEL   0xFF

Macro Definition Documentation

BDCR_REG

#define BDCR_REG   0x70

RCC_BDCR register offset.

NO_SEL

#define NO_SEL   0xFF

Dummy: Add a specificier when no selection is possible

RTC_SEL

#define RTC_SEL

(

val

)

STM32_CLOCK(val, 3, 8, BDCR_REG)

Device domain clocks selection helpers.

BDCR devices

STM32_CLOCK

#define STM32_CLOCK	(		val,
			mask,
			shift,
			reg
	)

Value:

        ((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) |            \
         (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) |      \
         (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) |         \
         (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT))

STM32_CLOCK_BUS_AHB1

#define STM32_CLOCK_BUS_AHB1   0x030

Domain clocks Bus clocks

STM32_CLOCK_BUS_AHB2

#define STM32_CLOCK_BUS_AHB2   0x034

STM32_CLOCK_BUS_AHB3

#define STM32_CLOCK_BUS_AHB3   0x038

STM32_CLOCK_BUS_APB1

#define STM32_CLOCK_BUS_APB1   0x040

STM32_CLOCK_BUS_APB2

#define STM32_CLOCK_BUS_APB2   0x044

STM32_CLOCK_BUS_APB3

#define STM32_CLOCK_BUS_APB3   0x0A8

STM32_CLOCK_MASK_MASK

#define STM32_CLOCK_MASK_MASK   0x7U

STM32_CLOCK_MASK_SHIFT

#define STM32_CLOCK_MASK_SHIFT   13U

STM32_CLOCK_REG_MASK

#define STM32_CLOCK_REG_MASK   0xFFU

STM32 clock configuration bit field.

• reg (1/2/3) [ 0 : 7 ]
• shift (0..31) [ 8 : 12 ]
• mask (0x1, 0x3, 0x7) [ 13 : 15 ]
• val (0..7) [ 16 : 18 ]

Parameters

reg	RCC_CFGRx register offset
shift	Position within RCC_CFGRx.
mask	Mask for the RCC_CFGRx field.
val	Clock value (0, 1, ... 7).

STM32_CLOCK_REG_SHIFT

#define STM32_CLOCK_REG_SHIFT   0U

STM32_CLOCK_SHIFT_MASK

#define STM32_CLOCK_SHIFT_MASK   0x1FU

STM32_CLOCK_SHIFT_SHIFT

#define STM32_CLOCK_SHIFT_SHIFT   8U

STM32_CLOCK_VAL_MASK

#define STM32_CLOCK_VAL_MASK   0x7U

STM32_CLOCK_VAL_SHIFT

#define STM32_CLOCK_VAL_SHIFT   16U

STM32_PERIPH_BUS_MAX

#define STM32_PERIPH_BUS_MAX   STM32_CLOCK_BUS_APB3

STM32_PERIPH_BUS_MIN

#define STM32_PERIPH_BUS_MIN   STM32_CLOCK_BUS_AHB1

STM32_SRC_LSE

#define STM32_SRC_LSE   0x004

Fixed clocks

STM32_SRC_LSI

#define STM32_SRC_LSI   0x005

STM32_SRC_PLL_P

#define STM32_SRC_PLL_P   0x001

Domain clocks PLL clock outputs

STM32_SRC_PLL_Q

#define STM32_SRC_PLL_Q   0x002

STM32_SRC_PLL_R

#define STM32_SRC_PLL_R   0x003

STM32_SRC_SYSCLK

#define STM32_SRC_SYSCLK   0x006

System clock