Zephyr Project API  3.4.0
A Scalable Open Source RTOS
Data Structures | Macros | Typedefs
arm_mpu_v7m.h File Reference

Go to the source code of this file.

Data Structures

struct  arm_mpu_region_attr
 
struct  k_mem_partition_attr_t
 

Macros

#define NO_ACCESS   0x0
 
#define NO_ACCESS_Msk   ((NO_ACCESS << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk)
 
#define P_NA_U_NA   0x0
 
#define P_NA_U_NA_Msk   ((P_NA_U_NA << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk)
 
#define P_RW_U_NA   0x1
 
#define P_RW_U_NA_Msk   ((P_RW_U_NA << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk)
 
#define P_RW_U_RO   0x2
 
#define P_RW_U_RO_Msk   ((P_RW_U_RO << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk)
 
#define P_RW_U_RW   0x3U
 
#define P_RW_U_RW_Msk   ((P_RW_U_RW << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk)
 
#define FULL_ACCESS   0x3
 
#define FULL_ACCESS_Msk   ((FULL_ACCESS << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk)
 
#define P_RO_U_NA   0x5
 
#define P_RO_U_NA_Msk   ((P_RO_U_NA << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk)
 
#define P_RO_U_RO   0x6
 
#define P_RO_U_RO_Msk   ((P_RO_U_RO << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk)
 
#define RO   0x7
 
#define RO_Msk   ((RO << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk)
 
#define NOT_EXEC   MPU_RASR_XN_Msk
 
#define STRONGLY_ORDERED_SHAREABLE   MPU_RASR_S_Msk
 
#define DEVICE_SHAREABLE   (MPU_RASR_B_Msk | MPU_RASR_S_Msk)
 
#define NORMAL_OUTER_INNER_WRITE_THROUGH_SHAREABLE    (MPU_RASR_C_Msk | MPU_RASR_S_Msk)
 
#define NORMAL_OUTER_INNER_WRITE_THROUGH_NON_SHAREABLE   MPU_RASR_C_Msk
 
#define NORMAL_OUTER_INNER_WRITE_BACK_SHAREABLE    (MPU_RASR_C_Msk | MPU_RASR_B_Msk | MPU_RASR_S_Msk)
 
#define NORMAL_OUTER_INNER_WRITE_BACK_NON_SHAREABLE    (MPU_RASR_C_Msk | MPU_RASR_B_Msk)
 
#define NORMAL_OUTER_INNER_NON_CACHEABLE_SHAREABLE    ((1 << MPU_RASR_TEX_Pos) | MPU_RASR_S_Msk)
 
#define NORMAL_OUTER_INNER_NON_CACHEABLE_NON_SHAREABLE    (1 << MPU_RASR_TEX_Pos)
 
#define NORMAL_OUTER_INNER_WRITE_BACK_WRITE_READ_ALLOCATE_SHAREABLE
 
#define NORMAL_OUTER_INNER_WRITE_BACK_WRITE_READ_ALLOCATE_NON_SHAREABLE    ((1 << MPU_RASR_TEX_Pos) | MPU_RASR_C_Msk | MPU_RASR_B_Msk)
 
#define DEVICE_NON_SHAREABLE   (2 << MPU_RASR_TEX_Pos)
 
#define SUB_REGION_0_DISABLED   ((0x01 << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk)
 
#define SUB_REGION_1_DISABLED   ((0x02 << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk)
 
#define SUB_REGION_2_DISABLED   ((0x04 << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk)
 
#define SUB_REGION_3_DISABLED   ((0x08 << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk)
 
#define SUB_REGION_4_DISABLED   ((0x10 << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk)
 
#define SUB_REGION_5_DISABLED   ((0x20 << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk)
 
#define SUB_REGION_6_DISABLED   ((0x40 << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk)
 
#define SUB_REGION_7_DISABLED   ((0x80 << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk)
 
#define REGION_SIZE(size)
 
#define REGION_32B   REGION_SIZE(32B)
 
#define REGION_64B   REGION_SIZE(64B)
 
#define REGION_128B   REGION_SIZE(128B)
 
#define REGION_256B   REGION_SIZE(256B)
 
#define REGION_512B   REGION_SIZE(512B)
 
#define REGION_1K   REGION_SIZE(1KB)
 
#define REGION_2K   REGION_SIZE(2KB)
 
#define REGION_4K   REGION_SIZE(4KB)
 
#define REGION_8K   REGION_SIZE(8KB)
 
#define REGION_16K   REGION_SIZE(16KB)
 
#define REGION_32K   REGION_SIZE(32KB)
 
#define REGION_64K   REGION_SIZE(64KB)
 
#define REGION_128K   REGION_SIZE(128KB)
 
#define REGION_256K   REGION_SIZE(256KB)
 
#define REGION_512K   REGION_SIZE(512KB)
 
#define REGION_1M   REGION_SIZE(1MB)
 
#define REGION_2M   REGION_SIZE(2MB)
 
#define REGION_4M   REGION_SIZE(4MB)
 
#define REGION_8M   REGION_SIZE(8MB)
 
#define REGION_16M   REGION_SIZE(16MB)
 
#define REGION_32M   REGION_SIZE(32MB)
 
#define REGION_64M   REGION_SIZE(64MB)
 
#define REGION_128M   REGION_SIZE(128MB)
 
#define REGION_256M   REGION_SIZE(256MB)
 
#define REGION_512M   REGION_SIZE(512MB)
 
#define REGION_1G   REGION_SIZE(1GB)
 
#define REGION_2G   REGION_SIZE(2GB)
 
#define REGION_4G   REGION_SIZE(4GB)
 
#define REGION_RAM_ATTR(size)
 
#define REGION_RAM_NOCACHE_ATTR(size)
 
#define REGION_FLASH_ATTR(size)
 
#define REGION_PPB_ATTR(size)
 
#define REGION_IO_ATTR(size)   { (DEVICE_NON_SHAREABLE | size | P_RW_U_NA_Msk) }
 
#define REGION_EXTMEM_ATTR(size)
 
#define K_MEM_PARTITION_P_NA_U_NA
 
#define K_MEM_PARTITION_P_RW_U_RW
 
#define K_MEM_PARTITION_P_RW_U_RO
 
#define K_MEM_PARTITION_P_RW_U_NA
 
#define K_MEM_PARTITION_P_RO_U_RO
 
#define K_MEM_PARTITION_P_RO_U_NA
 
#define K_MEM_PARTITION_P_RWX_U_RWX
 
#define K_MEM_PARTITION_P_RWX_U_RX
 
#define K_MEM_PARTITION_P_RX_U_RX
 
#define K_MEM_PARTITION_IS_WRITABLE(attr)
 
#define K_MEM_PARTITION_IS_EXECUTABLE(attr)    (!((attr.rasr_attr) & (NOT_EXEC)))
 
#define K_MEM_PARTITION_P_NA_U_NA_NOCACHE
 
#define K_MEM_PARTITION_P_RW_U_RW_NOCACHE
 
#define K_MEM_PARTITION_P_RW_U_RO_NOCACHE
 
#define K_MEM_PARTITION_P_RW_U_NA_NOCACHE
 
#define K_MEM_PARTITION_P_RO_U_RO_NOCACHE
 
#define K_MEM_PARTITION_P_RO_U_NA_NOCACHE
 
#define K_MEM_PARTITION_P_RWX_U_RWX_NOCACHE
 
#define K_MEM_PARTITION_P_RWX_U_RX_NOCACHE
 
#define K_MEM_PARTITION_P_RX_U_RX_NOCACHE
 

Typedefs

typedef struct arm_mpu_region_attr arm_mpu_region_attr_t
 

Macro Definition Documentation

◆ DEVICE_NON_SHAREABLE

#define DEVICE_NON_SHAREABLE   (2 << MPU_RASR_TEX_Pos)

◆ DEVICE_SHAREABLE

#define DEVICE_SHAREABLE   (MPU_RASR_B_Msk | MPU_RASR_S_Msk)

◆ FULL_ACCESS

#define FULL_ACCESS   0x3

◆ FULL_ACCESS_Msk

#define FULL_ACCESS_Msk   ((FULL_ACCESS << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk)

◆ K_MEM_PARTITION_IS_EXECUTABLE

#define K_MEM_PARTITION_IS_EXECUTABLE (   attr)     (!((attr.rasr_attr) & (NOT_EXEC)))

◆ K_MEM_PARTITION_IS_WRITABLE

#define K_MEM_PARTITION_IS_WRITABLE (   attr)
Value:
({ \
int __is_writable__; \
switch (attr.rasr_attr & MPU_RASR_AP_Msk) { \
case P_RW_U_RW_Msk: \
case P_RW_U_RO_Msk: \
case P_RW_U_NA_Msk: \
__is_writable__ = 1; \
break; \
default: \
__is_writable__ = 0; \
} \
__is_writable__; \
})
P_RW_U_NA_Msk
#define P_RW_U_NA_Msk
Definition: arm_mpu_v7m.h:27
P_RW_U_RO_Msk
#define P_RW_U_RO_Msk
Definition: arm_mpu_v7m.h:30
P_RW_U_RW_Msk
#define P_RW_U_RW_Msk
Definition: arm_mpu_v7m.h:33
MPU_RASR_AP_Msk
#define MPU_RASR_AP_Msk
Definition: mpu.h:21

◆ K_MEM_PARTITION_P_NA_U_NA

#define K_MEM_PARTITION_P_NA_U_NA
Value:
((k_mem_partition_attr_t) \
{ _K_MEM_PARTITION_P_NA_U_NA | \
NORMAL_OUTER_INNER_WRITE_BACK_WRITE_READ_ALLOCATE_NON_SHAREABLE})
k_mem_partition_attr_t
uint32_t k_mem_partition_attr_t
Definition: arch.h:226

◆ K_MEM_PARTITION_P_NA_U_NA_NOCACHE

#define K_MEM_PARTITION_P_NA_U_NA_NOCACHE
Value:
((k_mem_partition_attr_t) \
{(_K_MEM_PARTITION_P_NA_U_NA \
| NORMAL_OUTER_INNER_NON_CACHEABLE_SHAREABLE)})
NORMAL_OUTER_INNER_NON_CACHEABLE_SHAREABLE
#define NORMAL_OUTER_INNER_NON_CACHEABLE_SHAREABLE
Definition: arm_mpu_v7m.h:60

◆ K_MEM_PARTITION_P_RO_U_NA

#define K_MEM_PARTITION_P_RO_U_NA
Value:
((k_mem_partition_attr_t) \
{ _K_MEM_PARTITION_P_RO_U_NA | \
NORMAL_OUTER_INNER_WRITE_BACK_WRITE_READ_ALLOCATE_NON_SHAREABLE})

◆ K_MEM_PARTITION_P_RO_U_NA_NOCACHE

#define K_MEM_PARTITION_P_RO_U_NA_NOCACHE
Value:
((k_mem_partition_attr_t) \
{(_K_MEM_PARTITION_P_RO_U_NA \
| NORMAL_OUTER_INNER_NON_CACHEABLE_SHAREABLE)})

◆ K_MEM_PARTITION_P_RO_U_RO

#define K_MEM_PARTITION_P_RO_U_RO
Value:
((k_mem_partition_attr_t) \
{ _K_MEM_PARTITION_P_RO_U_RO | \
NORMAL_OUTER_INNER_WRITE_BACK_WRITE_READ_ALLOCATE_NON_SHAREABLE})

◆ K_MEM_PARTITION_P_RO_U_RO_NOCACHE

#define K_MEM_PARTITION_P_RO_U_RO_NOCACHE
Value:
((k_mem_partition_attr_t) \
{(_K_MEM_PARTITION_P_RO_U_RO \
| NORMAL_OUTER_INNER_NON_CACHEABLE_SHAREABLE)})

◆ K_MEM_PARTITION_P_RW_U_NA

#define K_MEM_PARTITION_P_RW_U_NA
Value:
((k_mem_partition_attr_t) \
{ _K_MEM_PARTITION_P_RW_U_NA | \
NORMAL_OUTER_INNER_WRITE_BACK_WRITE_READ_ALLOCATE_NON_SHAREABLE})

◆ K_MEM_PARTITION_P_RW_U_NA_NOCACHE

#define K_MEM_PARTITION_P_RW_U_NA_NOCACHE
Value:
((k_mem_partition_attr_t) \
{(_K_MEM_PARTITION_P_RW_U_NA \
| NORMAL_OUTER_INNER_NON_CACHEABLE_SHAREABLE)})

◆ K_MEM_PARTITION_P_RW_U_RO

#define K_MEM_PARTITION_P_RW_U_RO
Value:
((k_mem_partition_attr_t) \
{ _K_MEM_PARTITION_P_RW_U_RO | \
NORMAL_OUTER_INNER_WRITE_BACK_WRITE_READ_ALLOCATE_NON_SHAREABLE})

◆ K_MEM_PARTITION_P_RW_U_RO_NOCACHE

#define K_MEM_PARTITION_P_RW_U_RO_NOCACHE
Value:
((k_mem_partition_attr_t) \
{(_K_MEM_PARTITION_P_RW_U_RO \
| NORMAL_OUTER_INNER_NON_CACHEABLE_SHAREABLE)})

◆ K_MEM_PARTITION_P_RW_U_RW

#define K_MEM_PARTITION_P_RW_U_RW
Value:
((k_mem_partition_attr_t) \
{ _K_MEM_PARTITION_P_RW_U_RW | \
NORMAL_OUTER_INNER_WRITE_BACK_WRITE_READ_ALLOCATE_NON_SHAREABLE})

◆ K_MEM_PARTITION_P_RW_U_RW_NOCACHE

#define K_MEM_PARTITION_P_RW_U_RW_NOCACHE
Value:
((k_mem_partition_attr_t) \
{(_K_MEM_PARTITION_P_RW_U_RW \
| NORMAL_OUTER_INNER_NON_CACHEABLE_SHAREABLE)})

◆ K_MEM_PARTITION_P_RWX_U_RWX

#define K_MEM_PARTITION_P_RWX_U_RWX
Value:
((k_mem_partition_attr_t) \
{ _K_MEM_PARTITION_P_RWX_U_RWX | \
NORMAL_OUTER_INNER_WRITE_BACK_WRITE_READ_ALLOCATE_NON_SHAREABLE})

◆ K_MEM_PARTITION_P_RWX_U_RWX_NOCACHE

#define K_MEM_PARTITION_P_RWX_U_RWX_NOCACHE
Value:
((k_mem_partition_attr_t) \
{(_K_MEM_PARTITION_P_RWX_U_RWX \
| NORMAL_OUTER_INNER_NON_CACHEABLE_SHAREABLE)})

◆ K_MEM_PARTITION_P_RWX_U_RX

#define K_MEM_PARTITION_P_RWX_U_RX
Value:
((k_mem_partition_attr_t) \
{ _K_MEM_PARTITION_P_RWX_U_RX | \
NORMAL_OUTER_INNER_WRITE_BACK_WRITE_READ_ALLOCATE_NON_SHAREABLE})

◆ K_MEM_PARTITION_P_RWX_U_RX_NOCACHE

#define K_MEM_PARTITION_P_RWX_U_RX_NOCACHE
Value:
((k_mem_partition_attr_t) \
{(_K_MEM_PARTITION_P_RWX_U_RX \
| NORMAL_OUTER_INNER_NON_CACHEABLE_SHAREABLE)})

◆ K_MEM_PARTITION_P_RX_U_RX

#define K_MEM_PARTITION_P_RX_U_RX
Value:
((k_mem_partition_attr_t) \
{ _K_MEM_PARTITION_P_RX_U_RX | \
NORMAL_OUTER_INNER_WRITE_BACK_WRITE_READ_ALLOCATE_NON_SHAREABLE})

◆ K_MEM_PARTITION_P_RX_U_RX_NOCACHE

#define K_MEM_PARTITION_P_RX_U_RX_NOCACHE
Value:
((k_mem_partition_attr_t) \
{(_K_MEM_PARTITION_P_RX_U_RX \
| NORMAL_OUTER_INNER_NON_CACHEABLE_SHAREABLE)})

◆ NO_ACCESS

#define NO_ACCESS   0x0

◆ NO_ACCESS_Msk

#define NO_ACCESS_Msk   ((NO_ACCESS << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk)

◆ NORMAL_OUTER_INNER_NON_CACHEABLE_NON_SHAREABLE

#define NORMAL_OUTER_INNER_NON_CACHEABLE_NON_SHAREABLE    (1 << MPU_RASR_TEX_Pos)

◆ NORMAL_OUTER_INNER_NON_CACHEABLE_SHAREABLE

#define NORMAL_OUTER_INNER_NON_CACHEABLE_SHAREABLE    ((1 << MPU_RASR_TEX_Pos) | MPU_RASR_S_Msk)

◆ NORMAL_OUTER_INNER_WRITE_BACK_NON_SHAREABLE

#define NORMAL_OUTER_INNER_WRITE_BACK_NON_SHAREABLE    (MPU_RASR_C_Msk | MPU_RASR_B_Msk)

◆ NORMAL_OUTER_INNER_WRITE_BACK_SHAREABLE

#define NORMAL_OUTER_INNER_WRITE_BACK_SHAREABLE    (MPU_RASR_C_Msk | MPU_RASR_B_Msk | MPU_RASR_S_Msk)

◆ NORMAL_OUTER_INNER_WRITE_BACK_WRITE_READ_ALLOCATE_NON_SHAREABLE

#define NORMAL_OUTER_INNER_WRITE_BACK_WRITE_READ_ALLOCATE_NON_SHAREABLE    ((1 << MPU_RASR_TEX_Pos) | MPU_RASR_C_Msk | MPU_RASR_B_Msk)

◆ NORMAL_OUTER_INNER_WRITE_BACK_WRITE_READ_ALLOCATE_SHAREABLE

#define NORMAL_OUTER_INNER_WRITE_BACK_WRITE_READ_ALLOCATE_SHAREABLE
Value:
((1 << MPU_RASR_TEX_Pos) |\
MPU_RASR_C_Msk | MPU_RASR_B_Msk | MPU_RASR_S_Msk)
MPU_RASR_TEX_Pos
#define MPU_RASR_TEX_Pos
Definition: mpu.h:23
MPU_RASR_S_Msk
#define MPU_RASR_S_Msk
Definition: mpu.h:27
MPU_RASR_C_Msk
#define MPU_RASR_C_Msk
Definition: mpu.h:30
MPU_RASR_B_Msk
#define MPU_RASR_B_Msk
Definition: mpu.h:33

◆ NORMAL_OUTER_INNER_WRITE_THROUGH_NON_SHAREABLE

#define NORMAL_OUTER_INNER_WRITE_THROUGH_NON_SHAREABLE   MPU_RASR_C_Msk

◆ NORMAL_OUTER_INNER_WRITE_THROUGH_SHAREABLE

#define NORMAL_OUTER_INNER_WRITE_THROUGH_SHAREABLE    (MPU_RASR_C_Msk | MPU_RASR_S_Msk)

◆ NOT_EXEC

#define NOT_EXEC   MPU_RASR_XN_Msk

◆ P_NA_U_NA

#define P_NA_U_NA   0x0

◆ P_NA_U_NA_Msk

#define P_NA_U_NA_Msk   ((P_NA_U_NA << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk)

◆ P_RO_U_NA

#define P_RO_U_NA   0x5

◆ P_RO_U_NA_Msk

#define P_RO_U_NA_Msk   ((P_RO_U_NA << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk)

◆ P_RO_U_RO

#define P_RO_U_RO   0x6

◆ P_RO_U_RO_Msk

#define P_RO_U_RO_Msk   ((P_RO_U_RO << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk)

◆ P_RW_U_NA

#define P_RW_U_NA   0x1

◆ P_RW_U_NA_Msk

#define P_RW_U_NA_Msk   ((P_RW_U_NA << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk)

◆ P_RW_U_RO

#define P_RW_U_RO   0x2

◆ P_RW_U_RO_Msk

#define P_RW_U_RO_Msk   ((P_RW_U_RO << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk)

◆ P_RW_U_RW

#define P_RW_U_RW   0x3U

◆ P_RW_U_RW_Msk

#define P_RW_U_RW_Msk   ((P_RW_U_RW << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk)

◆ REGION_128B

#define REGION_128B   REGION_SIZE(128B)

◆ REGION_128K

#define REGION_128K   REGION_SIZE(128KB)

◆ REGION_128M

#define REGION_128M   REGION_SIZE(128MB)

◆ REGION_16K

#define REGION_16K   REGION_SIZE(16KB)

◆ REGION_16M

#define REGION_16M   REGION_SIZE(16MB)

◆ REGION_1G

#define REGION_1G   REGION_SIZE(1GB)

◆ REGION_1K

#define REGION_1K   REGION_SIZE(1KB)

◆ REGION_1M

#define REGION_1M   REGION_SIZE(1MB)

◆ REGION_256B

#define REGION_256B   REGION_SIZE(256B)

◆ REGION_256K

#define REGION_256K   REGION_SIZE(256KB)

◆ REGION_256M

#define REGION_256M   REGION_SIZE(256MB)

◆ REGION_2G

#define REGION_2G   REGION_SIZE(2GB)

◆ REGION_2K

#define REGION_2K   REGION_SIZE(2KB)

◆ REGION_2M

#define REGION_2M   REGION_SIZE(2MB)

◆ REGION_32B

#define REGION_32B   REGION_SIZE(32B)

◆ REGION_32K

#define REGION_32K   REGION_SIZE(32KB)

◆ REGION_32M

#define REGION_32M   REGION_SIZE(32MB)

◆ REGION_4G

#define REGION_4G   REGION_SIZE(4GB)

◆ REGION_4K

#define REGION_4K   REGION_SIZE(4KB)

◆ REGION_4M

#define REGION_4M   REGION_SIZE(4MB)

◆ REGION_512B

#define REGION_512B   REGION_SIZE(512B)

◆ REGION_512K

#define REGION_512K   REGION_SIZE(512KB)

◆ REGION_512M

#define REGION_512M   REGION_SIZE(512MB)

◆ REGION_64B

#define REGION_64B   REGION_SIZE(64B)

◆ REGION_64K

#define REGION_64K   REGION_SIZE(64KB)

◆ REGION_64M

#define REGION_64M   REGION_SIZE(64MB)

◆ REGION_8K

#define REGION_8K   REGION_SIZE(8KB)

◆ REGION_8M

#define REGION_8M   REGION_SIZE(8MB)

◆ REGION_EXTMEM_ATTR

#define REGION_EXTMEM_ATTR (   size)
Value:
{ (STRONGLY_ORDERED_SHAREABLE | size | \
NO_ACCESS_Msk) }
STRONGLY_ORDERED_SHAREABLE
#define STRONGLY_ORDERED_SHAREABLE
Definition: arm_mpu_v7m.h:51

◆ REGION_FLASH_ATTR

#define REGION_FLASH_ATTR (   size)
Value:
{ \
(NORMAL_OUTER_INNER_WRITE_THROUGH_NON_SHAREABLE | size | RO_Msk) \
}
NORMAL_OUTER_INNER_WRITE_THROUGH_NON_SHAREABLE
#define NORMAL_OUTER_INNER_WRITE_THROUGH_NON_SHAREABLE
Definition: arm_mpu_v7m.h:55
RO_Msk
#define RO_Msk
Definition: arm_mpu_v7m.h:45

◆ REGION_IO_ATTR

#define REGION_IO_ATTR (   size)    { (DEVICE_NON_SHAREABLE | size | P_RW_U_NA_Msk) }

◆ REGION_PPB_ATTR

#define REGION_PPB_ATTR (   size)
Value:
{ (STRONGLY_ORDERED_SHAREABLE | size | \
P_RW_U_NA_Msk) }

◆ REGION_RAM_ATTR

#define REGION_RAM_ATTR (   size)
Value:
{ \
(NORMAL_OUTER_INNER_WRITE_BACK_WRITE_READ_ALLOCATE_NON_SHAREABLE | \
MPU_RASR_XN_Msk | size | P_RW_U_NA_Msk) \
}
NORMAL_OUTER_INNER_WRITE_BACK_WRITE_READ_ALLOCATE_NON_SHAREABLE
#define NORMAL_OUTER_INNER_WRITE_BACK_WRITE_READ_ALLOCATE_NON_SHAREABLE
Definition: arm_mpu_v7m.h:67

◆ REGION_RAM_NOCACHE_ATTR

#define REGION_RAM_NOCACHE_ATTR (   size)
Value:
{ \
(NORMAL_OUTER_INNER_NON_CACHEABLE_NON_SHAREABLE | \
MPU_RASR_XN_Msk | size | P_RW_U_NA_Msk) \
}
NORMAL_OUTER_INNER_NON_CACHEABLE_NON_SHAREABLE
#define NORMAL_OUTER_INNER_NON_CACHEABLE_NON_SHAREABLE
Definition: arm_mpu_v7m.h:62

◆ REGION_SIZE

#define REGION_SIZE (   size)
Value:
((ARM_MPU_REGION_SIZE_ ## size \
<< MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk)
MPU_RASR_SIZE_Msk
#define MPU_RASR_SIZE_Msk
Definition: mpu.h:12
MPU_RASR_SIZE_Pos
#define MPU_RASR_SIZE_Pos
Definition: mpu.h:11

◆ RO

#define RO   0x7

◆ RO_Msk

#define RO_Msk   ((RO << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk)

◆ STRONGLY_ORDERED_SHAREABLE

#define STRONGLY_ORDERED_SHAREABLE   MPU_RASR_S_Msk

◆ SUB_REGION_0_DISABLED

#define SUB_REGION_0_DISABLED   ((0x01 << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk)

◆ SUB_REGION_1_DISABLED

#define SUB_REGION_1_DISABLED   ((0x02 << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk)

◆ SUB_REGION_2_DISABLED

#define SUB_REGION_2_DISABLED   ((0x04 << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk)

◆ SUB_REGION_3_DISABLED

#define SUB_REGION_3_DISABLED   ((0x08 << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk)

◆ SUB_REGION_4_DISABLED

#define SUB_REGION_4_DISABLED   ((0x10 << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk)

◆ SUB_REGION_5_DISABLED

#define SUB_REGION_5_DISABLED   ((0x20 << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk)

◆ SUB_REGION_6_DISABLED

#define SUB_REGION_6_DISABLED   ((0x40 << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk)

◆ SUB_REGION_7_DISABLED

#define SUB_REGION_7_DISABLED   ((0x80 << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk)

Typedef Documentation

◆ arm_mpu_region_attr_t

typedef struct arm_mpu_region_attr arm_mpu_region_attr_t