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Zephyr Project API 3.7.0
A Scalable Open Source RTOS
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Go to the source code of this file.
Macros | |
| #define | NRF_PSEL(fun, port, pin) |
| Utility macro to build nRF psels property entry. | |
| #define | NRF_PSEL_DISCONNECTED(fun) |
| Utility macro to build nRF psels property entry when a pin is disconnected. | |
nRF pin configuration bit field positions and masks. | |
| #define | NRF_FUN_POS 17U |
| Position of the function field. | |
| #define | NRF_FUN_MSK 0x7FFFU |
| Mask for the function field. | |
| #define | NRF_INVERT_POS 16U |
| Position of the invert field. | |
| #define | NRF_INVERT_MSK 0x1U |
| Mask for the invert field. | |
| #define | NRF_LP_POS 15U |
| Position of the low power field. | |
| #define | NRF_LP_MSK 0x1U |
| Mask for the low power field. | |
| #define | NRF_DRIVE_POS 11U |
| Position of the drive configuration field. | |
| #define | NRF_DRIVE_MSK 0xFU |
| Mask for the drive configuration field. | |
| #define | NRF_PULL_POS 9U |
| Position of the pull configuration field. | |
| #define | NRF_PULL_MSK 0x3U |
| Mask for the pull configuration field. | |
| #define | NRF_PIN_POS 0U |
| Position of the pin field. | |
| #define | NRF_PIN_MSK 0x1FFU |
| Mask for the pin field. | |
nRF pinctrl pin functions. | |
| #define | NRF_FUN_UART_TX 0U |
| UART TX. | |
| #define | NRF_FUN_UART_RX 1U |
| UART RX. | |
| #define | NRF_FUN_UART_RTS 2U |
| UART RTS. | |
| #define | NRF_FUN_UART_CTS 3U |
| UART CTS. | |
| #define | NRF_FUN_SPIM_SCK 4U |
| SPI master SCK. | |
| #define | NRF_FUN_SPIM_MOSI 5U |
| SPI master MOSI. | |
| #define | NRF_FUN_SPIM_MISO 6U |
| SPI master MISO. | |
| #define | NRF_FUN_SPIS_SCK 7U |
| SPI slave SCK. | |
| #define | NRF_FUN_SPIS_MOSI 8U |
| SPI slave MOSI. | |
| #define | NRF_FUN_SPIS_MISO 9U |
| SPI slave MISO. | |
| #define | NRF_FUN_SPIS_CSN 10U |
| SPI slave CSN. | |
| #define | NRF_FUN_TWIM_SCL 11U |
| TWI master SCL. | |
| #define | NRF_FUN_TWIM_SDA 12U |
| TWI master SDA. | |
| #define | NRF_FUN_I2S_SCK_M 13U |
| I2S SCK in master mode. | |
| #define | NRF_FUN_I2S_SCK_S 14U |
| I2S SCK in slave mode. | |
| #define | NRF_FUN_I2S_LRCK_M 15U |
| I2S LRCK in master mode. | |
| #define | NRF_FUN_I2S_LRCK_S 16U |
| I2S LRCK in slave mode. | |
| #define | NRF_FUN_I2S_SDIN 17U |
| I2S SDIN. | |
| #define | NRF_FUN_I2S_SDOUT 18U |
| I2S SDOUT. | |
| #define | NRF_FUN_I2S_MCK 19U |
| I2S MCK. | |
| #define | NRF_FUN_PDM_CLK 20U |
| PDM CLK. | |
| #define | NRF_FUN_PDM_DIN 21U |
| PDM DIN. | |
| #define | NRF_FUN_PWM_OUT0 22U |
| PWM OUT0. | |
| #define | NRF_FUN_PWM_OUT1 23U |
| PWM OUT1. | |
| #define | NRF_FUN_PWM_OUT2 24U |
| PWM OUT2. | |
| #define | NRF_FUN_PWM_OUT3 25U |
| PWM OUT3. | |
| #define | NRF_FUN_QDEC_A 26U |
| QDEC A. | |
| #define | NRF_FUN_QDEC_B 27U |
| QDEC B. | |
| #define | NRF_FUN_QDEC_LED 28U |
| QDEC LED. | |
| #define | NRF_FUN_QSPI_SCK 29U |
| QSPI SCK. | |
| #define | NRF_FUN_QSPI_CSN 30U |
| QSPI CSN. | |
| #define | NRF_FUN_QSPI_IO0 31U |
| QSPI IO0. | |
| #define | NRF_FUN_QSPI_IO1 32U |
| QSPI IO1. | |
| #define | NRF_FUN_QSPI_IO2 33U |
| QSPI IO2. | |
| #define | NRF_FUN_QSPI_IO3 34U |
| QSPI IO3. | |
| #define | NRF_FUN_EXMIF_CK 35U |
| EXMIF CK. | |
| #define | NRF_FUN_EXMIF_DQ0 36U |
| EXMIF DQ0. | |
| #define | NRF_FUN_EXMIF_DQ1 37U |
| EXMIF DQ1. | |
| #define | NRF_FUN_EXMIF_DQ2 38U |
| EXMIF DQ2. | |
| #define | NRF_FUN_EXMIF_DQ3 39U |
| EXMIF DQ3. | |
| #define | NRF_FUN_EXMIF_DQ4 40U |
| EXMIF DQ4. | |
| #define | NRF_FUN_EXMIF_DQ5 41U |
| EXMIF DQ5. | |
| #define | NRF_FUN_EXMIF_DQ6 42U |
| EXMIF DQ6. | |
| #define | NRF_FUN_EXMIF_DQ7 43U |
| EXMIF DQ7. | |
| #define | NRF_FUN_EXMIF_CS0 44U |
| EXMIF CS0. | |
| #define | NRF_FUN_EXMIF_CS1 45U |
| EXMIF CS1. | |
| #define | NRF_FUN_CAN_TX 46U |
| CAN TX. | |
| #define | NRF_FUN_CAN_RX 47U |
| CAN RX. | |
nRF pinctrl output drive. | |
| #define | NRF_DRIVE_S0S1 0U |
| Standard '0', standard '1'. | |
| #define | NRF_DRIVE_H0S1 1U |
| High drive '0', standard '1'. | |
| #define | NRF_DRIVE_S0H1 2U |
| Standard '0', high drive '1'. | |
| #define | NRF_DRIVE_H0H1 3U |
| High drive '0', high drive '1'. | |
| #define | NRF_DRIVE_D0S1 4U |
| Disconnect '0' standard '1'. | |
| #define | NRF_DRIVE_D0H1 5U |
| Disconnect '0', high drive '1'. | |
| #define | NRF_DRIVE_S0D1 6U |
| Standard '0', disconnect '1'. | |
| #define | NRF_DRIVE_H0D1 7U |
| High drive '0', disconnect '1'. | |
| #define | NRF_DRIVE_E0E1 8U |
| Extra high drive '0', extra high drive '1'. | |
nRF pinctrl pull-up/down. | |
| |
| #define | NRF_PULL_NONE 0U |
| Pull-up disabled. | |
| #define | NRF_PULL_DOWN 1U |
| Pull-down enabled. | |
| #define | NRF_PULL_UP 3U |
| Pull-up enabled. | |
nRF pinctrl low power mode. | |
| #define | NRF_LP_DISABLE 0U |
| Input. | |
| #define | NRF_LP_ENABLE 1U |
| Output. | |
nRF pinctrl helpers to indicate disconnected pins. | |
| #define | NRF_PIN_DISCONNECTED NRF_PIN_MSK |
| Indicates that a pin is disconnected. | |
| #define NRF_DRIVE_D0H1 5U |
Disconnect '0', high drive '1'.
| #define NRF_DRIVE_D0S1 4U |
Disconnect '0' standard '1'.
| #define NRF_DRIVE_E0E1 8U |
Extra high drive '0', extra high drive '1'.
| #define NRF_DRIVE_H0D1 7U |
High drive '0', disconnect '1'.
| #define NRF_DRIVE_H0H1 3U |
High drive '0', high drive '1'.
| #define NRF_DRIVE_H0S1 1U |
High drive '0', standard '1'.
| #define NRF_DRIVE_MSK 0xFU |
Mask for the drive configuration field.
| #define NRF_DRIVE_POS 11U |
Position of the drive configuration field.
| #define NRF_DRIVE_S0D1 6U |
Standard '0', disconnect '1'.
| #define NRF_DRIVE_S0H1 2U |
Standard '0', high drive '1'.
| #define NRF_DRIVE_S0S1 0U |
Standard '0', standard '1'.
| #define NRF_FUN_CAN_RX 47U |
CAN RX.
| #define NRF_FUN_CAN_TX 46U |
CAN TX.
| #define NRF_FUN_EXMIF_CK 35U |
EXMIF CK.
| #define NRF_FUN_EXMIF_CS0 44U |
EXMIF CS0.
| #define NRF_FUN_EXMIF_CS1 45U |
EXMIF CS1.
| #define NRF_FUN_EXMIF_DQ0 36U |
EXMIF DQ0.
| #define NRF_FUN_EXMIF_DQ1 37U |
EXMIF DQ1.
| #define NRF_FUN_EXMIF_DQ2 38U |
EXMIF DQ2.
| #define NRF_FUN_EXMIF_DQ3 39U |
EXMIF DQ3.
| #define NRF_FUN_EXMIF_DQ4 40U |
EXMIF DQ4.
| #define NRF_FUN_EXMIF_DQ5 41U |
EXMIF DQ5.
| #define NRF_FUN_EXMIF_DQ6 42U |
EXMIF DQ6.
| #define NRF_FUN_EXMIF_DQ7 43U |
EXMIF DQ7.
| #define NRF_FUN_I2S_LRCK_M 15U |
I2S LRCK in master mode.
| #define NRF_FUN_I2S_LRCK_S 16U |
I2S LRCK in slave mode.
| #define NRF_FUN_I2S_MCK 19U |
I2S MCK.
| #define NRF_FUN_I2S_SCK_M 13U |
I2S SCK in master mode.
| #define NRF_FUN_I2S_SCK_S 14U |
I2S SCK in slave mode.
| #define NRF_FUN_I2S_SDIN 17U |
I2S SDIN.
| #define NRF_FUN_I2S_SDOUT 18U |
I2S SDOUT.
| #define NRF_FUN_MSK 0x7FFFU |
Mask for the function field.
| #define NRF_FUN_PDM_CLK 20U |
PDM CLK.
| #define NRF_FUN_PDM_DIN 21U |
PDM DIN.
| #define NRF_FUN_POS 17U |
Position of the function field.
| #define NRF_FUN_PWM_OUT0 22U |
PWM OUT0.
| #define NRF_FUN_PWM_OUT1 23U |
PWM OUT1.
| #define NRF_FUN_PWM_OUT2 24U |
PWM OUT2.
| #define NRF_FUN_PWM_OUT3 25U |
PWM OUT3.
| #define NRF_FUN_QDEC_A 26U |
QDEC A.
| #define NRF_FUN_QDEC_B 27U |
QDEC B.
| #define NRF_FUN_QDEC_LED 28U |
QDEC LED.
| #define NRF_FUN_QSPI_CSN 30U |
QSPI CSN.
| #define NRF_FUN_QSPI_IO0 31U |
QSPI IO0.
| #define NRF_FUN_QSPI_IO1 32U |
QSPI IO1.
| #define NRF_FUN_QSPI_IO2 33U |
QSPI IO2.
| #define NRF_FUN_QSPI_IO3 34U |
QSPI IO3.
| #define NRF_FUN_QSPI_SCK 29U |
QSPI SCK.
| #define NRF_FUN_SPIM_MISO 6U |
SPI master MISO.
| #define NRF_FUN_SPIM_MOSI 5U |
SPI master MOSI.
| #define NRF_FUN_SPIM_SCK 4U |
SPI master SCK.
| #define NRF_FUN_SPIS_CSN 10U |
SPI slave CSN.
| #define NRF_FUN_SPIS_MISO 9U |
SPI slave MISO.
| #define NRF_FUN_SPIS_MOSI 8U |
SPI slave MOSI.
| #define NRF_FUN_SPIS_SCK 7U |
SPI slave SCK.
| #define NRF_FUN_TWIM_SCL 11U |
TWI master SCL.
| #define NRF_FUN_TWIM_SDA 12U |
TWI master SDA.
| #define NRF_FUN_UART_CTS 3U |
UART CTS.
| #define NRF_FUN_UART_RTS 2U |
UART RTS.
| #define NRF_FUN_UART_RX 1U |
UART RX.
| #define NRF_FUN_UART_TX 0U |
UART TX.
| #define NRF_INVERT_MSK 0x1U |
Mask for the invert field.
| #define NRF_INVERT_POS 16U |
Position of the invert field.
| #define NRF_LP_DISABLE 0U |
Input.
| #define NRF_LP_ENABLE 1U |
Output.
| #define NRF_LP_MSK 0x1U |
Mask for the low power field.
| #define NRF_LP_POS 15U |
Position of the low power field.
| #define NRF_PIN_DISCONNECTED NRF_PIN_MSK |
Indicates that a pin is disconnected.
| #define NRF_PIN_MSK 0x1FFU |
Mask for the pin field.
| #define NRF_PIN_POS 0U |
Position of the pin field.
| #define NRF_PSEL | ( | fun, | |
| port, | |||
| pin | |||
| ) |
Utility macro to build nRF psels property entry.
| fun | Pin function configuration (see NRF_FUNC_{name} macros). |
| port | Port (0 or 15). |
| pin | Pin (0..31). |
| #define NRF_PSEL_DISCONNECTED | ( | fun | ) |
Utility macro to build nRF psels property entry when a pin is disconnected.
This can be useful in situations where code running before Zephyr, e.g. a bootloader configures pins that later needs to be disconnected.
| fun | Pin function configuration (see NRF_FUN_{name} macros). |
| #define NRF_PULL_DOWN 1U |
Pull-down enabled.
| #define NRF_PULL_MSK 0x3U |
Mask for the pull configuration field.
| #define NRF_PULL_NONE 0U |
Pull-up disabled.
| #define NRF_PULL_POS 9U |
Position of the pull configuration field.
| #define NRF_PULL_UP 3U |
Pull-up enabled.