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#define | FIELD_POS(field) field##_POS |
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#define | FIELD_SIZE(field) field##_SIZE |
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#define | GET_FIELD(reg, field) _GET_FIELD_(reg, FIELD_POS(field), FIELD_SIZE(field)) |
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#define | SET_FIELD(reg, field, value) _SET_FIELD_(reg, FIELD_POS(field), FIELD_SIZE(field), value) |
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#define | GET_FIELD_POS(field) _GET_FIELD_POS_(FIELD_POS(field)) |
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#define | GET_FIELD_SZ(field) _GET_FIELD_SZ_(FIELD_SIZE(field)) |
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#define | SC16IS75X_REG_RHR 0x00 |
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#define | SC16IS75X_REG_THR 0x00 |
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#define | SC16IS75X_REG_IER 0x01 |
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#define | SC16IS75X_BIT_IER_RXHSENA 0 |
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#define | SC16IS75X_BIT_IER_TXHSENA 1 |
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#define | SC16IS75X_BIT_IER_RXLSENA 2 |
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#define | SC16IS75X_BIT_IER_MSENA 3 |
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#define | SC16IS75X_BIT_IER_SLEEPENA 4 |
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#define | SC16IS75X_BIT_IER_XOFFENA 5 |
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#define | SC16IS75X_BIT_IER_RTSENA 6 |
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#define | SC16IS75X_BIT_IER_CTSENA 7 |
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#define | SC16IS75X_REG_FCR 0x02 |
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#define | SC16IS75X_BIT_FCR_FIFOENA 0 |
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#define | SC16IS75X_BIT_FCR_RXFIFORST 1 |
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#define | SC16IS75X_BIT_FCR_TXFIFORST 2 |
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#define | SC16IS75X_BIT_FCR_TXFIFOTRIG 4 |
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#define | SC16IS75X_TXFIFOTRIG_8SP 0b00 |
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#define | SC16IS75X_TXFIFOTRIG_16SP 0b01 |
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#define | SC16IS75X_TXFIFOTRIG_32SP 0b10 |
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#define | SC16IS75X_TXFIFOTRIG_56SP 0b11 |
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#define | SC16IS75X_BIT_FCR_RXFIFOTRIG 6 |
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#define | SC16IS75X_RXFIFOTRIG_8CH 0b00 |
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#define | SC16IS75X_RXFIFOTRIG_16CH 0b01 |
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#define | SC16IS75X_RXFIFOTRIG_56CH 0b10 |
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#define | SC16IS75X_RXFIFOTRIG_60CH 0b11 |
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#define | SC16IS75X_REG_IIR 0x02 |
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#define | SC16IS75X_BIT_IIR_PENDING 0 |
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#define | SC16IS75X_BIT_IIR_TYPE_POS 1 |
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#define | SC16IS75X_BIT_IIR_TYPE_SIZE 5 |
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#define | SC16IS75X_INT_RXLSE 0b00011 |
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#define | SC16IS75X_INT_RXTO 0b00110 |
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#define | SC16IS75X_INT_RHRI 0b00010 |
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#define | SC16IS75X_INT_THRI 0b00001 |
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#define | SC16IS75X_INT_MSI 0b00000 |
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#define | SC16IS75X_INT_IO 0b11000 |
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#define | SC16IS75X_INT_XOFF 0b01000 |
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#define | SC16IS75X_INT_HWFL 0b10000 |
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#define | SC16IS75X_BIT_IIR_MIRROR_FIFOENA_POS 6 |
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#define | SC16IS75X_BIT_IIR_MIRROR_FIFOENA_SIZE 2 |
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#define | SC16IS75X_INT_FIFOENA 0b11 |
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#define | SC16IS75X_REG_LCR 0x03 |
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#define | SC16IS75X_BIT_LCR_WORD_LEN_POS 0 |
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#define | SC16IS75X_BIT_LCR_WORD_LEN_SIZE 2 |
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#define | SC16IS75X_WORD_LEN_5 0b00 |
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#define | SC16IS75X_WORD_LEN_6 0b01 |
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#define | SC16IS75X_WORD_LEN_7 0b10 |
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#define | SC16IS75X_WORD_LEN_8 0b11 |
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#define | SC16IS75X_BIT_LCR_STOP_LEN_POS 2 |
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#define | SC16IS75X_BIT_LCR_STOP_LEN_SIZE 1 |
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#define | SC16IS75X_STOP_LEN_1 0b0 |
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#define | SC16IS75X_STOP_LEN_1_5 0b1 |
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#define | SC16IS75X_STOP_LEN_2 0b1 |
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#define | SC16IS75X_BIT_LCR_PARITY_POS 3 |
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#define | SC16IS75X_BIT_LCR_PARITY_SIZE 3 |
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#define | SC16IS75X_PARITY_NONE 0b000 |
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#define | SC16IS75X_PARITY_ODD 0b001 |
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#define | SC16IS75X_PARITY_EVEN 0b011 |
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#define | SC16IS75X_PARITY_MARK 0b101 |
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#define | SC16IS75X_PARITY_SPACE 0b111 |
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#define | SC16IS75X_BIT_LCR_TX_LINE_BREAK 6 |
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#define | SC16IS75X_BIT_LCR_DLENA 7 |
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#define | SC16IS75X_BIT_LCR_ACCESS_EFR 0b10111111 /* 0xBF */ |
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#define | SC16IS75X_REG_MCR 0x04 |
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#define | SC16IS75X_BIT_MCR_DTR 0 |
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#define | SC16IS75X_BIT_MCR_RTS 1 |
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#define | SC16IS75X_BIT_MCR_TCRTLRENA 2 |
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#define | SC16IS75X_BIT_MCR_LOOPBACK 4 |
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#define | SC16IS75X_BIT_MCR_XONANY 5 |
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#define | SC16IS75X_BIT_MCR_IRDAENA 6 |
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#define | SC16IS75X_BIT_MCR_CLKDIV 7 |
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#define | SC16IS75X_REG_LSR 0x05 |
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#define | SC16IS75X_BIT_LSR_RX_DATA 0 |
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#define | SC16IS75X_BIT_LSR_RX_OVERRUN 1 |
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#define | SC16IS75X_BIT_LSR_RX_PARITY 2 |
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#define | SC16IS75X_BIT_LSR_RX_FRAMING 3 |
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#define | SC16IS75X_BIT_LSR_RX_LINE_BREAK 4 |
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#define | SC16IS75X_BIT_LSR_THREMPTY 5 |
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#define | SC16IS75X_BIT_LSR_THRTSREMPTY 6 |
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#define | SC16IS75X_BIT_LSR_RX_FIFO 7 |
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#define | SC16IS75X_REG_MSR 0x06 |
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#define | SC16IS75X_BIT_MSR_CTS_CHANGED 0 |
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#define | SC16IS75X_BIT_MSR_DSR_CHANGED 1 |
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#define | SC16IS75X_BIT_MSR_RI_CHANGED 2 |
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#define | SC16IS75X_BIT_MSR_CD_CHANGED 3 |
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#define | SC16IS75X_BIT_MSR_CTS 4 |
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#define | SC16IS75X_BIT_MSR_DSR 5 |
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#define | SC16IS75X_BIT_MSR_RI 6 |
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#define | SC16IS75X_BIT_MSR_CD 7 |
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#define | SC16IS75X_REG_SPR 0x07 |
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#define | SC16IS75X_REG_TCR 0x06 |
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#define | SC16IS75X_REG_TLR 0x07 |
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#define | SC16IS75X_REG_TXLVL 0x08 |
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#define | SC16IS75X_BIT_TXLVL_SP_POS 0 |
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#define | SC16IS75X_BIT_TXLVL_SP_SIZE 7 |
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#define | SC16IS75X_REG_RXLVL 0x09 |
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#define | SC16IS75X_BIT_RXLVL_CH_POS 0 |
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#define | SC16IS75X_BIT_RXLVL_CH_SIZE 7 |
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#define | SC16IS75X_REG_IODIR 0x0A |
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#define | SC16IS75X_REG_IOSTATE 0x0B |
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#define | SC16IS75X_REG_IOINTENA 0x0C |
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#define | SC16IS75X_REG_IOCONTROL 0x0E |
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#define | SC16IS75X_BIT_IOCONTROL_IOLATCH 0 |
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#define | SC16IS75X_BIT_IOCONTROL_MODEM_PINS_A 1 |
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#define | SC16IS75X_BIT_IOCONTROL_MODEM_PINS_B 2 |
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#define | SC16IS75X_BIT_IOCONTROL_SRESET 3 |
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#define | SC16IS75X_REG_EFCR 0x0F |
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#define | SC16IS75X_BIT_EFCR_RS485 0 |
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#define | SC16IS75X_BIT_EFCR_RXDISABLE 1 |
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#define | SC16IS75X_BIT_EFCR_TXDISABLE 2 |
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#define | SC16IS75X_BIT_EFCR_RTSCON 4 |
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#define | SC16IS75X_BIT_EFCR_RTSINVER 5 |
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#define | SC16IS75X_BIT_EFCR_IRDA 7 |
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#define | SC16IS75X_REG_DLL 0x00 |
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#define | SC16IS75X_REG_DLH 0x01 |
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#define | SC16IS75X_REG_EFR 0x02 |
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#define | SC16IS75X_BIT_EFR_RX_SWFLOWCTRL_POS 0 |
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#define | SC16IS75X_BIT_EFR_RX_SWFLOWCTRL_SIZE 2 |
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#define | SC16IS75X_BIT_EFR_TX_SWFLOWCTRL_POS 2 |
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#define | SC16IS75X_BIT_EFR_TX_SWFLOWCTRL_SIZE 2 |
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#define | SC16IS75X_SWFLOWCTRL_NONE 0b00 |
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#define | SC16IS75X_SWFLOWCTRL_XONOFF1 0b10 |
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#define | SC16IS75X_SWFLOWCTRL_XONOFF2 0b01 |
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#define | SC16IS75X_SWFLOWCTRL_XONOFF12 0b11 |
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#define | SC16IS75X_BIT_EFR_EFENA 4 |
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#define | SC16IS75X_BIT_EFR_XOFF2ENA 5 |
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#define | SC16IS75X_BIT_EFR_RTSENA 6 |
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#define | SC16IS75X_BIT_EFR_CTSENA 7 |
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#define | SC16IS75X_REG_XON1 0x04 |
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#define | SC16IS75X_REG_XON2 0x05 |
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#define | SC16IS75X_REG_XOFF1 0x06 |
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#define | SC16IS75X_REG_XOFF2 0x07 |
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#define | SC16IS75X_FIFO_CAPACITY 64 |
| FIFO capacity in byte.
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#define | SC16IS75X_IO_NUM_PINS_MAX 8 |
| Maximum programmable I/O pins.
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#define | SC16IS75X_UART_CHANNELS_MAX 2 |
| Maximum UART channels.
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#define | READ_SC16IS75X_REG(dev, reg, val) mfd_sc16is75x_read_register((dev), 0, SC16IS75X_REG_##reg, (val)); |
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#define | READ_SC16IS75X_CHREG(dev, ch, reg, val) mfd_sc16is75x_read_register((dev), (ch), SC16IS75X_REG_##reg, (val)); |
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#define | WRITE_SC16IS75X_REG(dev, reg, val) mfd_sc16is75x_write_register((dev), 0, SC16IS75X_REG_##reg, (val)); |
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#define | WRITE_SC16IS75X_CHREG(dev, ch, reg, val) mfd_sc16is75x_write_register((dev), (ch), SC16IS75X_REG_##reg, (val)); |
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#define | SETBIT_SC16IS75X_REG(dev, reg, bit, val) |
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#define | SETBIT_SC16IS75X_CHREG(dev, ch, reg, bit, val) |
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int | mfd_sc16is75x_read_register (const struct device *dev, const uint8_t channel, const uint8_t reg, uint8_t *value) |
| Read from an internal register.
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int | mfd_sc16is75x_write_register (const struct device *dev, const uint8_t channel, const uint8_t reg, const uint8_t value) |
| Write to an internal register.
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int | mfd_sc16is75x_set_register_bit (const struct device *dev, const uint8_t channel, const uint8_t reg, const uint8_t bit, const bool value) |
| Enable or disable a bit in an internal register.
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int | mfd_sc16is75x_read_fifo (const struct device *dev, const uint8_t channel, uint8_t *buf, const size_t len) |
| Read data from FIFO.
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int | mfd_sc16is75x_write_fifo (const struct device *dev, const uint8_t channel, const uint8_t *buf, const size_t len) |
| Write data to FIFO.
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MFD Interface for an SC16IS75X bridge.