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◆ AD7124_ADC_AIN0
| #define AD7124_ADC_AIN0 0 |
◆ AD7124_ADC_AIN1
| #define AD7124_ADC_AIN1 1 |
◆ AD7124_ADC_AIN10
| #define AD7124_ADC_AIN10 10 |
◆ AD7124_ADC_AIN11
| #define AD7124_ADC_AIN11 11 |
◆ AD7124_ADC_AIN12
| #define AD7124_ADC_AIN12 12 |
◆ AD7124_ADC_AIN13
| #define AD7124_ADC_AIN13 13 |
◆ AD7124_ADC_AIN14
| #define AD7124_ADC_AIN14 14 |
◆ AD7124_ADC_AIN15
| #define AD7124_ADC_AIN15 15 |
◆ AD7124_ADC_AIN2
| #define AD7124_ADC_AIN2 2 |
◆ AD7124_ADC_AIN3
| #define AD7124_ADC_AIN3 3 |
◆ AD7124_ADC_AIN4
| #define AD7124_ADC_AIN4 4 |
◆ AD7124_ADC_AIN5
| #define AD7124_ADC_AIN5 5 |
◆ AD7124_ADC_AIN6
| #define AD7124_ADC_AIN6 6 |
◆ AD7124_ADC_AIN7
| #define AD7124_ADC_AIN7 7 |
◆ AD7124_ADC_AIN8
| #define AD7124_ADC_AIN8 8 |
◆ AD7124_ADC_AIN9
| #define AD7124_ADC_AIN9 9 |
◆ AD7124_ADC_ALDO_AVSS_DIV6_MINUS
| #define AD7124_ADC_ALDO_AVSS_DIV6_MINUS 25 |
◆ AD7124_ADC_ALDO_AVSS_DIV6_PLUS
| #define AD7124_ADC_ALDO_AVSS_DIV6_PLUS 24 |
◆ AD7124_ADC_AVDD_AVSS_DIV6_MINUS
| #define AD7124_ADC_AVDD_AVSS_DIV6_MINUS 21 |
◆ AD7124_ADC_AVDD_AVSS_DIV6_PLUS
| #define AD7124_ADC_AVDD_AVSS_DIV6_PLUS 20 |
◆ AD7124_ADC_AVSS
| #define AD7124_ADC_AVSS 17 |
◆ AD7124_ADC_DGND
| #define AD7124_ADC_DGND 19 |
◆ AD7124_ADC_DLDO_DGND_DIV6_MINUS
| #define AD7124_ADC_DLDO_DGND_DIV6_MINUS 27 |
◆ AD7124_ADC_DLDO_DGND_DIV6_PLUS
| #define AD7124_ADC_DLDO_DGND_DIV6_PLUS 26 |
◆ AD7124_ADC_INTERNAL_REF
| #define AD7124_ADC_INTERNAL_REF 18 |
◆ AD7124_ADC_IOVDD_DGND_DIV6_MINUS
| #define AD7124_ADC_IOVDD_DGND_DIV6_MINUS 23 |
◆ AD7124_ADC_IOVDD_DGND_DIV6_PLUS
| #define AD7124_ADC_IOVDD_DGND_DIV6_PLUS 22 |
◆ AD7124_ADC_TEMP_SENSOR
| #define AD7124_ADC_TEMP_SENSOR 16 |
◆ AD7124_ADC_V_20MV_M
| #define AD7124_ADC_V_20MV_M 29 |
◆ AD7124_ADC_V_20MV_P
| #define AD7124_ADC_V_20MV_P 28 |
◆ AD7124_IOUT0_0_1_UA
| #define AD7124_IOUT0_0_1_UA 07 |
◆ AD7124_IOUT0_1000_UA
| #define AD7124_IOUT0_1000_UA 06 |
◆ AD7124_IOUT0_100_UA
| #define AD7124_IOUT0_100_UA 02 |
◆ AD7124_IOUT0_250_UA
| #define AD7124_IOUT0_250_UA 03 |
◆ AD7124_IOUT0_500_UA
| #define AD7124_IOUT0_500_UA 04 |
◆ AD7124_IOUT0_50_UA
| #define AD7124_IOUT0_50_UA 01 |
◆ AD7124_IOUT0_750_UA
| #define AD7124_IOUT0_750_UA 05 |
◆ AD7124_IOUT0_OFF
| #define AD7124_IOUT0_OFF 00 |
◆ AD7124_IOUT1_0_1_UA
| #define AD7124_IOUT1_0_1_UA 0F |
◆ AD7124_IOUT1_1000_UA
| #define AD7124_IOUT1_1000_UA 0E |
◆ AD7124_IOUT1_100_UA
| #define AD7124_IOUT1_100_UA 0A |
◆ AD7124_IOUT1_250_UA
| #define AD7124_IOUT1_250_UA 0B |
◆ AD7124_IOUT1_500_UA
| #define AD7124_IOUT1_500_UA 0C |
◆ AD7124_IOUT1_50_UA
| #define AD7124_IOUT1_50_UA 09 |
◆ AD7124_IOUT1_750_UA
| #define AD7124_IOUT1_750_UA 0D |
◆ AD7124_IOUT1_OFF
| #define AD7124_IOUT1_OFF 08 |
◆ AD7124_IOUT_CH_AIN0
| #define AD7124_IOUT_CH_AIN0 00 |
◆ AD7124_IOUT_CH_AIN1
| #define AD7124_IOUT_CH_AIN1 01 |
◆ AD7124_IOUT_CH_AIN2
| #define AD7124_IOUT_CH_AIN2 04 |
◆ AD7124_IOUT_CH_AIN3
| #define AD7124_IOUT_CH_AIN3 05 |
◆ AD7124_IOUT_CH_AIN4
| #define AD7124_IOUT_CH_AIN4 0A |
◆ AD7124_IOUT_CH_AIN5
| #define AD7124_IOUT_CH_AIN5 0B |
◆ AD7124_IOUT_CH_AIN6
| #define AD7124_IOUT_CH_AIN6 0E |
◆ AD7124_IOUT_CH_AIN7
| #define AD7124_IOUT_CH_AIN7 0F |