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Zephyr Project API 4.4.99
A Scalable Open Source RTOS
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Zephyr Project API 4.4.99
A Scalable Open Source RTOS
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Texas Instruments ADS1220 ADC driver API. More...
Go to the source code of this file.
Macros | |
| #define | ADS1220_RESOLUTION 24u |
| ADC resolution in bits. | |
| #define | ADS1220_CHANNELS 4u |
| Number of input channels. | |
| #define | ADS1220_CHANNEL_ID 0x00u |
| Device ID register value. | |
| #define | ADS1220_REG0_MUX_MSK 0xF0u |
| Mask for MUX field in configuration register 0. | |
| #define | ADS1220_REG0_MUX_AIN0_AIN1 (0x0u << 0x04) |
| MUX: AINP=AIN0, AINN=AIN1. | |
| #define | ADS1220_REG0_MUX_AIN0_AIN2 (0x1u << 0x04) |
| MUX: AINP=AIN0, AINN=AIN2. | |
| #define | ADS1220_REG0_MUX_AIN0_AIN3 (0x2u << 0x04) |
| MUX: AINP=AIN0, AINN=AIN3. | |
| #define | ADS1220_REG0_MUX_AIN1_AIN2 (0x3u << 0x04) |
| MUX: AINP=AIN1, AINN=AIN2. | |
| #define | ADS1220_REG0_MUX_AIN1_AIN3 (0x4u << 0x04) |
| MUX: AINP=AIN1, AINN=AIN3. | |
| #define | ADS1220_REG0_MUX_AIN2_AIN3 (0x5u << 0x04) |
| MUX: AINP=AIN2, AINN=AIN3. | |
| #define | ADS1220_REG0_MUX_AIN1_AIN0 (0x6u << 0x04) |
| MUX: AINP=AIN1, AINN=AIN0. | |
| #define | ADS1220_REG0_MUX_AIN3_AIN2 (0x7u << 0x04) |
| MUX: AINP=AIN3, AINN=AIN2. | |
| #define | ADS1220_REG0_MUX_AIN0_AVSS (0x8u << 0x04) |
| MUX: AINP=AIN0, AINN=AVSS. | |
| #define | ADS1220_REG0_MUX_AIN1_AVSS (0x9u << 0x04) |
| MUX: AINP=AIN1, AINN=AVSS. | |
| #define | ADS1220_REG0_MUX_AIN2_AVSS (0xAu << 0x04) |
| MUX: AINP=AIN2, AINN=AVSS. | |
| #define | ADS1220_REG0_MUX_AIN3_AVSS (0xBu << 0x04) |
| MUX: AINP=AIN3, AINN=AVSS. | |
| #define | ADS1220_REG0_MUX_V_REF (0xCu << 0x04) |
| MUX: (V_REFPx - V_REFNx) / 4 monitor. | |
| #define | ADS1220_REG0_MUX_AVDD_AVSS_1 (0xDu << 0x04) |
| MUX: (AVDD - AVSS) / 4 monitor. | |
| #define | ADS1220_REG0_MUX_AVDD_AVSS_2 (0xEu << 0x04) |
| MUX: AINP and AINN shorted to (AVDD + AVSS) / 2. | |
| #define | ADS1220_REG0_MUX_RESERVED (0xFu << 0x04) |
| MUX: Reserved. | |
| #define | ADS1220_REG0_GAIN_MSK 0x0Eu |
| Mask for GAIN field in configuration register 0. | |
| #define | ADS1220_REG0_GAIN_1 (0x0u << 0x01) |
| PGA gain = 1. | |
| #define | ADS1220_REG0_GAIN_2 (0x1u << 0x01) |
| PGA gain = 2. | |
| #define | ADS1220_REG0_GAIN_4 (0x2u << 0x01) |
| PGA gain = 4. | |
| #define | ADS1220_REG0_GAIN_8 (0x3u << 0x01) |
| PGA gain = 8. | |
| #define | ADS1220_REG0_GAIN_16 (0x4u << 0x01) |
| PGA gain = 16. | |
| #define | ADS1220_REG0_GAIN_32 (0x5u << 0x01) |
| PGA gain = 32. | |
| #define | ADS1220_REG0_GAIN_64 (0x6u << 0x01) |
| PGA gain = 64. | |
| #define | ADS1220_REG0_GAIN_128 (0x7u << 0x01) |
| PGA gain = 128. | |
| #define | ADS1220_REG0_PGA_BYPASS BIT(0) |
| PGA bypass bit in configuration register 0. | |
| #define | ADS1220_REG1_DR_MSK 0xE0u |
| Mask for DR field in configuration register 1. | |
| #define | ADS1220_REG1_DR_POS 0x5u |
| Bit position of DR field in configuration register 1. | |
| #define | ADS1220_REG1_MODE_MSK 0x18u |
| Mask for MODE field in configuration register 1. | |
| #define | ADS1220_REG1_MODE_POS 0x3u |
| Bit position of MODE field in configuration register 1. | |
| #define | ADS1220_REG1_MODE_NORMAL (0x0u << 0x03) |
| Operating mode: normal. | |
| #define | ADS1220_REG1_MODE_DUTY_CYCLE (0x1u << 0x03) |
| Operating mode: duty-cycle. | |
| #define | ADS1220_REG1_MODE_TURBO (0x2u << 0x03) |
| Operating mode: turbo. | |
| #define | ADS1220_REG1_CM BIT(2) |
| Conversion mode bit in configuration register 1. | |
| #define | ADS1220_REG1_TS BIT(1) |
| Temperature sensor mode bit in configuration register 1. | |
| #define | ADS1220_REG1_BCS BIT(0) |
| Burn-out current sources bit in configuration register 1. | |
| #define | ADS1220_REG2_VREF_MSK 0xC0u |
| Mask for VREF field in configuration register 2. | |
| #define | ADS1220_REG2_VREF_INT (0x0u << 0x06) |
| VREF: internal 2.048V reference. | |
| #define | ADS1220_REG2_VREF_EXT_0 (0x1u << 0x06) |
| VREF: external reference 0 (REFP0/REFN0). | |
| #define | ADS1220_REG2_VREF_EXT_1 (0x2u << 0x06) |
| VREF: external reference 1 (REFP1/REFN1). | |
| #define | ADS1220_REG2_VREF_SUPPLY (0x3u << 0x06) |
| VREF: analog supply (AVDD - AVSS). | |
| #define | ADS1220_REG2_50_60HZ_MSK 0x30u |
| Mask for 50/60Hz rejection filter in configuration register 2. | |
| #define | ADS1220_REG2_50_60HZ_NONE (0x0u << 0x04) |
| 50/60Hz filter: no rejection | |
| #define | ADS1220_REG2_50_60HZ_50HZ (0x1u << 0x04) |
| 50/60Hz filter: reject 50Hz only | |
| #define | ADS1220_REG2_50_60HZ_60HZ (0x2u << 0x04) |
| 50/60Hz filter: reject 60Hz only | |
| #define | ADS1220_REG2_50_60HZ_BOTH (0x3u << 0x04) |
| 50/60Hz filter: reject both 50Hz and 60Hz | |
| #define | ADS1220_REG2_PSW BIT(3) |
| Low-side power switch bit in configuration register 2. | |
| #define | ADS1220_REG2_IDAC_MSK 0x07u |
| Mask for IDAC current field in configuration register 2. | |
| #define | ADS1220_REG2_IDAC_OFF (0x0u) |
| IDAC current: off. | |
| #define | ADS1220_REG2_IDAC_10UA (0x1u) |
| IDAC current: 10 uA. | |
| #define | ADS1220_REG2_IDAC_50UA (0x2u) |
| IDAC current: 50 uA. | |
| #define | ADS1220_REG2_IDAC_100UA (0x3u) |
| IDAC current: 100 uA. | |
| #define | ADS1220_REG2_IDAC_250UA (0x4u) |
| IDAC current: 250 uA. | |
| #define | ADS1220_REG2_IDAC_500UA (0x5u) |
| IDAC current: 500 uA. | |
| #define | ADS1220_REG2_IDAC_1000UA (0x6u) |
| IDAC current: 1000 uA. | |
| #define | ADS1220_REG2_IDAC_1500UA (0x7u) |
| IDAC current: 1500 uA. | |
| #define | ADS1220_REG3_I1MUX_MSK 0xE0u |
| Mask for I1MUX field in configuration register 3. | |
| #define | ADS1220_REG3_I1MUX_POS 0x5u |
| Bit position of I1MUX field in configuration register 3. | |
| #define | ADS1220_REG3_I1MUX_DISABLED (0x0u << 0x05) |
| I1MUX: IDAC1 disabled. | |
| #define | ADS1220_REG3_I1MUX_AIN0_REFP1 (0x1u << 0x05) |
| I1MUX: IDAC1 connected to AIN0/REFP1. | |
| #define | ADS1220_REG3_I1MUX_AIN1 (0x2u << 0x05) |
| I1MUX: IDAC1 connected to AIN1. | |
| #define | ADS1220_REG3_I1MUX_AIN2 (0x3u << 0x05) |
| I1MUX: IDAC1 connected to AIN2. | |
| #define | ADS1220_REG3_I1MUX_AIN3_REFN1 (0x4u << 0x05) |
| I1MUX: IDAC1 connected to AIN3/REFN1. | |
| #define | ADS1220_REG3_I1MUX_REFP (0x5u << 0x05) |
| I1MUX: IDAC1 connected to REFP0. | |
| #define | ADS1220_REG3_I1MUX_REFN (0x6u << 0x05) |
| I1MUX: IDAC1 connected to REFN0. | |
| #define | ADS1220_REG3_I2MUX_MSK 0x1Cu |
| Mask for I2MUX field in configuration register 3. | |
| #define | ADS1220_REG3_I2MUX_POS 0x2u |
| Bit position of I2MUX field in configuration register 3. | |
| #define | ADS1220_REG3_I2MUX_DISABLED (0x0u << 0x02) |
| I2MUX: IDAC2 disabled. | |
| #define | ADS1220_REG3_I2MUX_AIN0_REFP1 (0x1u << 0x02) |
| I2MUX: IDAC2 connected to AIN0/REFP1. | |
| #define | ADS1220_REG3_I2MUX_AIN1 (0x2u << 0x02) |
| I2MUX: IDAC2 connected to AIN1. | |
| #define | ADS1220_REG3_I2MUX_AIN2 (0x3u << 0x02) |
| I2MUX: IDAC2 connected to AIN2. | |
| #define | ADS1220_REG3_I2MUX_AIN3_REFN1 (0x4u << 0x02) |
| I2MUX: IDAC2 connected to AIN3/REFN1. | |
| #define | ADS1220_REG3_I2MUX_REFP (0x5u << 0x02) |
| I2MUX: IDAC2 connected to REFP0. | |
| #define | ADS1220_REG3_I2MUX_REFN (0x6u << 0x02) |
| I2MUX: IDAC2 connected to REFN0. | |
| #define | ADS1220_REG3_DRDYM BIT(1) |
| DRDY mode bit in configuration register 3. | |
| #define | ADS1220_REG3_RESERVED BIT(0) |
| Reserved bit in configuration register 3. | |
Texas Instruments ADS1220 ADC driver API.
This file contains the API for the ADS1220 24-bit, 4-channel, low-power, Delta-Sigma ADC with integrated PGA, VREF, SPI interface, and two IDACs.
1.16.1