6#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ALIF_BALLETTO_CLOCKS_H_
7#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ALIF_BALLETTO_CLOCKS_H_
25#define ALIF_UART_CTRL_REG 0x08U
28#define ALIF_I2C0_CTRL_REG 0x50U
31#define ALIF_I2C1_CTRL_REG 0x54U
34#define ALIF_TIMER_CLKSEL_REG 0x04U
44#define ALIF_UART0_SYST_PCLK \
45 ALIF_CLK_CFG(CLKCTL_PER_SLV, UART_CTRL, 0U, 1U, 1U, 1U, 8U, ALIF_PARENT_CLK_SYST_PCLK)
47#define ALIF_UART1_SYST_PCLK \
48 ALIF_CLK_CFG(CLKCTL_PER_SLV, UART_CTRL, 1U, 1U, 1U, 1U, 9U, ALIF_PARENT_CLK_SYST_PCLK)
50#define ALIF_UART2_SYST_PCLK \
51 ALIF_CLK_CFG(CLKCTL_PER_SLV, UART_CTRL, 2U, 1U, 1U, 1U, 10U, ALIF_PARENT_CLK_SYST_PCLK)
53#define ALIF_UART3_SYST_PCLK \
54 ALIF_CLK_CFG(CLKCTL_PER_SLV, UART_CTRL, 3U, 1U, 1U, 1U, 11U, ALIF_PARENT_CLK_SYST_PCLK)
56#define ALIF_UART4_SYST_PCLK \
57 ALIF_CLK_CFG(CLKCTL_PER_SLV, UART_CTRL, 4U, 1U, 1U, 1U, 12U, ALIF_PARENT_CLK_SYST_PCLK)
59#define ALIF_UART5_SYST_PCLK \
60 ALIF_CLK_CFG(CLKCTL_PER_SLV, UART_CTRL, 5U, 1U, 1U, 1U, 13U, ALIF_PARENT_CLK_SYST_PCLK)
70#define ALIF_I2C0_SYST_PCLK \
71 ALIF_CLK_CFG(CLKCTL_PER_SLV, I2C0_CTRL, 0U, 1U, 0U, 0U, 0U, ALIF_PARENT_CLK_SYST_PCLK)
73#define ALIF_I2C1_SYST_PCLK \
74 ALIF_CLK_CFG(CLKCTL_PER_SLV, I2C1_CTRL, 0U, 1U, 0U, 0U, 0U, ALIF_PARENT_CLK_SYST_PCLK)
88#define ALIF_LPTIMER0_S32K_CLK \
89 ALIF_CLK_CFG(VBAT, TIMER_CLKSEL, 0U, 0U, 0U, 2U, 0U, ALIF_PARENT_CLK_S32K)
91#define ALIF_LPTIMER0_128K_CLK \
92 ALIF_CLK_CFG(VBAT, TIMER_CLKSEL, 0U, 0U, 1U, 2U, 0U, ALIF_PARENT_CLK_128K)
94#define ALIF_LPTIMER1_S32K_CLK \
95 ALIF_CLK_CFG(VBAT, TIMER_CLKSEL, 0U, 0U, 0U, 2U, 4U, ALIF_PARENT_CLK_S32K)
97#define ALIF_LPTIMER1_128K_CLK \
98 ALIF_CLK_CFG(VBAT, TIMER_CLKSEL, 0U, 0U, 1U, 2U, 4U, ALIF_PARENT_CLK_128K)
Common clock definitions for Alif Semiconductor SoC families.