Zephyr Project API
4.4.99
A Scalable Open Source RTOS
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alif-balletto-clocks.h
Go to the documentation of this file.
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/*
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* SPDX-FileCopyrightText: Copyright Alif Semiconductor
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ALIF_BALLETTO_CLOCKS_H_
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#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ALIF_BALLETTO_CLOCKS_H_
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#include "
alif-clocks-common.h
"
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#define ALIF_UART_CTRL_REG 0x08U
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#define ALIF_I2C0_CTRL_REG 0x50U
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#define ALIF_I2C1_CTRL_REG 0x54U
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#define ALIF_UART0_SYST_PCLK \
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ALIF_CLK_CFG(CLKCTL_PER_SLV, UART_CTRL, 0U, 1U, 1U, 1U, 8U, ALIF_PARENT_CLK_SYST_PCLK)
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#define ALIF_UART1_SYST_PCLK \
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ALIF_CLK_CFG(CLKCTL_PER_SLV, UART_CTRL, 1U, 1U, 1U, 1U, 9U, ALIF_PARENT_CLK_SYST_PCLK)
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#define ALIF_UART2_SYST_PCLK \
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ALIF_CLK_CFG(CLKCTL_PER_SLV, UART_CTRL, 2U, 1U, 1U, 1U, 10U, ALIF_PARENT_CLK_SYST_PCLK)
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#define ALIF_UART3_SYST_PCLK \
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ALIF_CLK_CFG(CLKCTL_PER_SLV, UART_CTRL, 3U, 1U, 1U, 1U, 11U, ALIF_PARENT_CLK_SYST_PCLK)
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#define ALIF_UART4_SYST_PCLK \
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ALIF_CLK_CFG(CLKCTL_PER_SLV, UART_CTRL, 4U, 1U, 1U, 1U, 12U, ALIF_PARENT_CLK_SYST_PCLK)
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#define ALIF_UART5_SYST_PCLK \
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ALIF_CLK_CFG(CLKCTL_PER_SLV, UART_CTRL, 5U, 1U, 1U, 1U, 13U, ALIF_PARENT_CLK_SYST_PCLK)
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#define ALIF_I2C0_SYST_PCLK \
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ALIF_CLK_CFG(CLKCTL_PER_SLV, I2C0_CTRL, 0U, 1U, 0U, 0U, 0U, ALIF_PARENT_CLK_SYST_PCLK)
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#define ALIF_I2C1_SYST_PCLK \
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ALIF_CLK_CFG(CLKCTL_PER_SLV, I2C1_CTRL, 0U, 1U, 0U, 0U, 0U, ALIF_PARENT_CLK_SYST_PCLK)
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#endif
/* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ALIF_BALLETTO_CLOCKS_H_ */
alif-clocks-common.h
Common clock definitions for Alif Semiconductor SoC families.
include
zephyr
dt-bindings
clock
alif-balletto-clocks.h
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