alif-balletto-clocks.h File Reference

Clock IDs for Alif Balletto SoC family. More...

#include "alif-clocks-common.h"

Go to the source code of this file.

Macros
Register offsets
#define	ALIF_UART_CTRL_REG   0x08U
	UART control register offset in CLKCTL_PER_SLV.
#define	ALIF_I2C0_CTRL_REG   0x50U
	I2C0 control register offset in CLKCTL_PER_SLV.
#define	ALIF_I2C1_CTRL_REG   0x54U
	I2C1 control register offset in CLKCTL_PER_SLV.
#define	ALIF_TIMER_CLKSEL_REG   0x04U
	LPTIMER clock select register offset in VBAT.
UART peripheral clocks
#define	ALIF_UART0_SYST_PCLK   ALIF_CLK_CFG(CLKCTL_PER_SLV, UART_CTRL, 0U, 1U, 1U, 1U, 8U, ALIF_PARENT_CLK_SYST_PCLK)
	UART0 clock sourced from system PCLK.
#define	ALIF_UART1_SYST_PCLK   ALIF_CLK_CFG(CLKCTL_PER_SLV, UART_CTRL, 1U, 1U, 1U, 1U, 9U, ALIF_PARENT_CLK_SYST_PCLK)
	UART1 clock sourced from system PCLK.
#define	ALIF_UART2_SYST_PCLK   ALIF_CLK_CFG(CLKCTL_PER_SLV, UART_CTRL, 2U, 1U, 1U, 1U, 10U, ALIF_PARENT_CLK_SYST_PCLK)
	UART2 clock sourced from system PCLK.
#define	ALIF_UART3_SYST_PCLK   ALIF_CLK_CFG(CLKCTL_PER_SLV, UART_CTRL, 3U, 1U, 1U, 1U, 11U, ALIF_PARENT_CLK_SYST_PCLK)
	UART3 clock sourced from system PCLK.
#define	ALIF_UART4_SYST_PCLK   ALIF_CLK_CFG(CLKCTL_PER_SLV, UART_CTRL, 4U, 1U, 1U, 1U, 12U, ALIF_PARENT_CLK_SYST_PCLK)
	UART4 clock sourced from system PCLK.
#define	ALIF_UART5_SYST_PCLK   ALIF_CLK_CFG(CLKCTL_PER_SLV, UART_CTRL, 5U, 1U, 1U, 1U, 13U, ALIF_PARENT_CLK_SYST_PCLK)
	UART5 clock sourced from system PCLK.
I2C peripheral clocks
#define	ALIF_I2C0_SYST_PCLK   ALIF_CLK_CFG(CLKCTL_PER_SLV, I2C0_CTRL, 0U, 1U, 0U, 0U, 0U, ALIF_PARENT_CLK_SYST_PCLK)
	I2C0 clock sourced from system PCLK.
#define	ALIF_I2C1_SYST_PCLK   ALIF_CLK_CFG(CLKCTL_PER_SLV, I2C1_CTRL, 0U, 1U, 0U, 0U, 0U, ALIF_PARENT_CLK_SYST_PCLK)
	I2C1 clock sourced from system PCLK.
LPTIMER peripheral clocks
The channels have no clock enable bit; only the source selection is programmed.
#define	ALIF_LPTIMER0_S32K_CLK   ALIF_CLK_CFG(VBAT, TIMER_CLKSEL, 0U, 0U, 0U, 2U, 0U, ALIF_PARENT_CLK_S32K)
	LPTIMER0 clock sourced from S32K_CLK.
#define	ALIF_LPTIMER0_128K_CLK   ALIF_CLK_CFG(VBAT, TIMER_CLKSEL, 0U, 0U, 1U, 2U, 0U, ALIF_PARENT_CLK_128K)
	LPTIMER0 clock sourced from 128K_CLK.
#define	ALIF_LPTIMER1_S32K_CLK   ALIF_CLK_CFG(VBAT, TIMER_CLKSEL, 0U, 0U, 0U, 2U, 4U, ALIF_PARENT_CLK_S32K)
	LPTIMER1 clock sourced from S32K_CLK.
#define	ALIF_LPTIMER1_128K_CLK   ALIF_CLK_CFG(VBAT, TIMER_CLKSEL, 0U, 0U, 1U, 2U, 4U, ALIF_PARENT_CLK_128K)
	LPTIMER1 clock sourced from 128K_CLK.

Detailed Description

Clock IDs for Alif Balletto SoC family.

Defines peripheral clock identifiers for the Alif Balletto family. Each clock ID is encoded using ALIF_CLK_CFG() macro from alif-clocks-common.h.

Macro Definition Documentation

ALIF_I2C0_CTRL_REG

#define ALIF_I2C0_CTRL_REG   0x50U

I2C0 control register offset in CLKCTL_PER_SLV.

ALIF_I2C0_SYST_PCLK

#define ALIF_I2C0_SYST_PCLK   ALIF_CLK_CFG(CLKCTL_PER_SLV, I2C0_CTRL, 0U, 1U, 0U, 0U, 0U, ALIF_PARENT_CLK_SYST_PCLK)

I2C0 clock sourced from system PCLK.

ALIF_I2C1_CTRL_REG

#define ALIF_I2C1_CTRL_REG   0x54U

I2C1 control register offset in CLKCTL_PER_SLV.

ALIF_I2C1_SYST_PCLK

#define ALIF_I2C1_SYST_PCLK   ALIF_CLK_CFG(CLKCTL_PER_SLV, I2C1_CTRL, 0U, 1U, 0U, 0U, 0U, ALIF_PARENT_CLK_SYST_PCLK)

I2C1 clock sourced from system PCLK.

ALIF_LPTIMER0_128K_CLK

#define ALIF_LPTIMER0_128K_CLK   ALIF_CLK_CFG(VBAT, TIMER_CLKSEL, 0U, 0U, 1U, 2U, 0U, ALIF_PARENT_CLK_128K)

LPTIMER0 clock sourced from 128K_CLK.

ALIF_LPTIMER0_S32K_CLK

#define ALIF_LPTIMER0_S32K_CLK   ALIF_CLK_CFG(VBAT, TIMER_CLKSEL, 0U, 0U, 0U, 2U, 0U, ALIF_PARENT_CLK_S32K)

LPTIMER0 clock sourced from S32K_CLK.

ALIF_LPTIMER1_128K_CLK

#define ALIF_LPTIMER1_128K_CLK   ALIF_CLK_CFG(VBAT, TIMER_CLKSEL, 0U, 0U, 1U, 2U, 4U, ALIF_PARENT_CLK_128K)

LPTIMER1 clock sourced from 128K_CLK.

ALIF_LPTIMER1_S32K_CLK

#define ALIF_LPTIMER1_S32K_CLK   ALIF_CLK_CFG(VBAT, TIMER_CLKSEL, 0U, 0U, 0U, 2U, 4U, ALIF_PARENT_CLK_S32K)

LPTIMER1 clock sourced from S32K_CLK.

ALIF_TIMER_CLKSEL_REG

#define ALIF_TIMER_CLKSEL_REG   0x04U

LPTIMER clock select register offset in VBAT.

ALIF_UART0_SYST_PCLK

#define ALIF_UART0_SYST_PCLK   ALIF_CLK_CFG(CLKCTL_PER_SLV, UART_CTRL, 0U, 1U, 1U, 1U, 8U, ALIF_PARENT_CLK_SYST_PCLK)

UART0 clock sourced from system PCLK.

ALIF_UART1_SYST_PCLK

#define ALIF_UART1_SYST_PCLK   ALIF_CLK_CFG(CLKCTL_PER_SLV, UART_CTRL, 1U, 1U, 1U, 1U, 9U, ALIF_PARENT_CLK_SYST_PCLK)

UART1 clock sourced from system PCLK.

ALIF_UART2_SYST_PCLK

#define ALIF_UART2_SYST_PCLK   ALIF_CLK_CFG(CLKCTL_PER_SLV, UART_CTRL, 2U, 1U, 1U, 1U, 10U, ALIF_PARENT_CLK_SYST_PCLK)

UART2 clock sourced from system PCLK.

ALIF_UART3_SYST_PCLK

#define ALIF_UART3_SYST_PCLK   ALIF_CLK_CFG(CLKCTL_PER_SLV, UART_CTRL, 3U, 1U, 1U, 1U, 11U, ALIF_PARENT_CLK_SYST_PCLK)

UART3 clock sourced from system PCLK.

ALIF_UART4_SYST_PCLK

#define ALIF_UART4_SYST_PCLK   ALIF_CLK_CFG(CLKCTL_PER_SLV, UART_CTRL, 4U, 1U, 1U, 1U, 12U, ALIF_PARENT_CLK_SYST_PCLK)

UART4 clock sourced from system PCLK.

ALIF_UART5_SYST_PCLK

#define ALIF_UART5_SYST_PCLK   ALIF_CLK_CFG(CLKCTL_PER_SLV, UART_CTRL, 5U, 1U, 1U, 1U, 13U, ALIF_PARENT_CLK_SYST_PCLK)

UART5 clock sourced from system PCLK.

ALIF_UART_CTRL_REG

#define ALIF_UART_CTRL_REG   0x08U

UART control register offset in CLKCTL_PER_SLV.