ameba_dma.h

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/*
 * Copyright (c) 2026 Realtek Semiconductor Corp.
 *
 * SPDX-License-Identifier: Apache-2.0
 */
 
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_AMEBA_DMA_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_AMEBA_DMA_H_



#define AMEBA_DMA_CH_DIR_SET(val) ((val & 0x3) << 0)

#define AMEBA_DMA_MEMORY_TO_MEMORY AMEBA_DMA_CH_DIR_SET(0)

#define AMEBA_DMA_MEMORY_TO_PERIPH AMEBA_DMA_CH_DIR_SET(1)

#define AMEBA_DMA_PERIPH_TO_MEMORY AMEBA_DMA_CH_DIR_SET(2)

#define AMEBA_DMA_PERIPH_TO_PERIPH AMEBA_DMA_CH_DIR_SET(3)

#define AMEBA_DMA_SRC_ADDR_ADJ_SET(val) ((val & 0x3) << 2)

#define AMEBA_DMA_SRC_ADDR_ADJ_INC AMEBA_DMA_SRC_ADDR_ADJ_SET(0)

#define AMEBA_DMA_SRC_ADDR_ADJ_NO_CHANGE AMEBA_DMA_SRC_ADDR_ADJ_SET(2)

#define AMEBA_DMA_DST_ADDR_ADJ_SET(val) ((val & 0x3) << 4)

#define AMEBA_DMA_DST_ADDR_ADJ_INC AMEBA_DMA_DST_ADDR_ADJ_SET(0)

#define AMEBA_DMA_DST_ADDR_ADJ_NO_CHANGE AMEBA_DMA_DST_ADDR_ADJ_SET(2)

#define AMEBA_DMA_SRC_DATA_SIZE_SET(val) ((val & 0x7) << 6)

#define AMEBA_DMA_SRC_WIDTH_8BITS AMEBA_DMA_SRC_DATA_SIZE_SET(0)

#define AMEBA_DMA_SRC_WIDTH_16BITS AMEBA_DMA_SRC_DATA_SIZE_SET(1)

#define AMEBA_DMA_SRC_WIDTH_32BITS AMEBA_DMA_SRC_DATA_SIZE_SET(2)

#define AMEBA_DMA_DST_DATA_SIZE_SET(val) ((val & 0x7) << 9)

#define AMEBA_DMA_DST_WIDTH_8BITS AMEBA_DMA_DST_DATA_SIZE_SET(0)

#define AMEBA_DMA_DST_WIDTH_16BITS AMEBA_DMA_DST_DATA_SIZE_SET(1)

#define AMEBA_DMA_DST_WIDTH_32BITS AMEBA_DMA_DST_DATA_SIZE_SET(2)

#define AMEBA_DMA_SRC_BURST_SET(val) ((val & 0x1F) << 12)

#define AMEBA_DMA_SRC_BURST_ONE AMEBA_DMA_SRC_BURST_SET(0)

#define AMEBA_DMA_SRC_BURST_FOUR AMEBA_DMA_SRC_BURST_SET(1)

#define AMEBA_DMA_SRC_BURST_EIGHT AMEBA_DMA_SRC_BURST_SET(2)

#define AMEBA_DMA_SRC_BURST_SIXTEEN AMEBA_DMA_SRC_BURST_SET(3)

#define AMEBA_DMA_DST_BURST_SET(val) ((val & 0x1F) << 17)

#define AMEBA_DMA_DST_BURST_ONE AMEBA_DMA_DST_BURST_SET(0)

#define AMEBA_DMA_DST_BURST_FOUR AMEBA_DMA_DST_BURST_SET(1)

#define AMEBA_DMA_DST_BURST_EIGHT AMEBA_DMA_DST_BURST_SET(2)

#define AMEBA_DMA_DST_BURST_SIXTEEN AMEBA_DMA_DST_BURST_SET(3)

#define AMEBA_DMA_CH_PRIORITY_SET(val) ((val & 0x7) << 22)

#define AMEBA_DMA_PERIPH_TX                                                                        \
        (AMEBA_DMA_MEMORY_TO_PERIPH | AMEBA_DMA_SRC_ADDR_ADJ_INC | AMEBA_DMA_DST_ADDR_ADJ_NO_CHANGE)

#define AMEBA_DMA_PERIPH_RX                                                                        \
        (AMEBA_DMA_PERIPH_TO_MEMORY | AMEBA_DMA_SRC_ADDR_ADJ_NO_CHANGE | AMEBA_DMA_DST_ADDR_ADJ_INC)

 
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_AMEBA_DMA_H_ */