ameba_dma.h File Reference

Ameba SoC DMA devicetree binding flags. More...

Go to the source code of this file.

Macros
DMA channel configuration flags
#define	AMEBA_DMA_CH_DIR_SET(val)
	Set DMA transfer direction bits [1:0].
#define	AMEBA_DMA_MEMORY_TO_MEMORY   AMEBA_DMA_CH_DIR_SET(0)
	DMA transfer direction: memory to memory.
#define	AMEBA_DMA_MEMORY_TO_PERIPH   AMEBA_DMA_CH_DIR_SET(1)
	DMA transfer direction: memory to peripheral.
#define	AMEBA_DMA_PERIPH_TO_MEMORY   AMEBA_DMA_CH_DIR_SET(2)
	DMA transfer direction: peripheral to memory.
#define	AMEBA_DMA_PERIPH_TO_PERIPH   AMEBA_DMA_CH_DIR_SET(3)
	DMA transfer direction: peripheral to peripheral.
#define	AMEBA_DMA_SRC_ADDR_ADJ_SET(val)
	Set source address adjustment bits [3:2].
#define	AMEBA_DMA_SRC_ADDR_ADJ_INC   AMEBA_DMA_SRC_ADDR_ADJ_SET(0)
	Source address increment after each transfer.
#define	AMEBA_DMA_SRC_ADDR_ADJ_NO_CHANGE   AMEBA_DMA_SRC_ADDR_ADJ_SET(2)
	Source address does not change.
#define	AMEBA_DMA_DST_ADDR_ADJ_SET(val)
	Set destination address adjustment bits [5:4].
#define	AMEBA_DMA_DST_ADDR_ADJ_INC   AMEBA_DMA_DST_ADDR_ADJ_SET(0)
	Destination address increment after each transfer.
#define	AMEBA_DMA_DST_ADDR_ADJ_NO_CHANGE   AMEBA_DMA_DST_ADDR_ADJ_SET(2)
	Destination address does not change.
#define	AMEBA_DMA_SRC_DATA_SIZE_SET(val)
	Set source data width bits [8:6].
#define	AMEBA_DMA_SRC_WIDTH_8BITS   AMEBA_DMA_SRC_DATA_SIZE_SET(0)
	Source data width: 8 bits.
#define	AMEBA_DMA_SRC_WIDTH_16BITS   AMEBA_DMA_SRC_DATA_SIZE_SET(1)
	Source data width: 16 bits.
#define	AMEBA_DMA_SRC_WIDTH_32BITS   AMEBA_DMA_SRC_DATA_SIZE_SET(2)
	Source data width: 32 bits.
#define	AMEBA_DMA_DST_DATA_SIZE_SET(val)
	Set destination data width bits [11:9].
#define	AMEBA_DMA_DST_WIDTH_8BITS   AMEBA_DMA_DST_DATA_SIZE_SET(0)
	Destination data width: 8 bits.
#define	AMEBA_DMA_DST_WIDTH_16BITS   AMEBA_DMA_DST_DATA_SIZE_SET(1)
	Destination data width: 16 bits.
#define	AMEBA_DMA_DST_WIDTH_32BITS   AMEBA_DMA_DST_DATA_SIZE_SET(2)
	Destination data width: 32 bits.
#define	AMEBA_DMA_SRC_BURST_SET(val)
	Set source burst length bits [16:12].
#define	AMEBA_DMA_SRC_BURST_ONE   AMEBA_DMA_SRC_BURST_SET(0)
	Source burst length: 1 transfer.
#define	AMEBA_DMA_SRC_BURST_FOUR   AMEBA_DMA_SRC_BURST_SET(1)
	Source burst length: 4 transfers.
#define	AMEBA_DMA_SRC_BURST_EIGHT   AMEBA_DMA_SRC_BURST_SET(2)
	Source burst length: 8 transfers.
#define	AMEBA_DMA_SRC_BURST_SIXTEEN   AMEBA_DMA_SRC_BURST_SET(3)
	Source burst length: 16 transfers.
#define	AMEBA_DMA_DST_BURST_SET(val)
	Set destination burst length bits [21:17].
#define	AMEBA_DMA_DST_BURST_ONE   AMEBA_DMA_DST_BURST_SET(0)
	Destination burst length: 1 transfer.
#define	AMEBA_DMA_DST_BURST_FOUR   AMEBA_DMA_DST_BURST_SET(1)
	Destination burst length: 4 transfers.
#define	AMEBA_DMA_DST_BURST_EIGHT   AMEBA_DMA_DST_BURST_SET(2)
	Destination burst length: 8 transfers.
#define	AMEBA_DMA_DST_BURST_SIXTEEN   AMEBA_DMA_DST_BURST_SET(3)
	Destination burst length: 16 transfers.
#define	AMEBA_DMA_CH_PRIORITY_SET(val)
	Set channel priority bits [24:22].
#define	AMEBA_DMA_PERIPH_TX   (AMEBA_DMA_MEMORY_TO_PERIPH | AMEBA_DMA_SRC_ADDR_ADJ_INC | AMEBA_DMA_DST_ADDR_ADJ_NO_CHANGE)
	Typical peripheral TX configuration.
#define	AMEBA_DMA_PERIPH_RX   (AMEBA_DMA_PERIPH_TO_MEMORY | AMEBA_DMA_SRC_ADDR_ADJ_NO_CHANGE | AMEBA_DMA_DST_ADDR_ADJ_INC)
	Typical peripheral RX configuration.

Detailed Description

Ameba SoC DMA devicetree binding flags.

This file defines bitfield flags used to configure DMA channels in devicetree for Ameba SoCs.

Macro Definition Documentation

AMEBA_DMA_CH_DIR_SET

#define AMEBA_DMA_CH_DIR_SET

(

val

)

Value:

((val & 0x3) << 0)

Set DMA transfer direction bits [1:0].

Parameters

val	Direction value encoded in bits [1:0].

AMEBA_DMA_CH_PRIORITY_SET

#define AMEBA_DMA_CH_PRIORITY_SET

(

val

)

Value:

((val & 0x7) << 22)

Set channel priority bits [24:22].

Parameters

val	Channel priority value in range 0–7.

AMEBA_DMA_DST_ADDR_ADJ_INC

#define AMEBA_DMA_DST_ADDR_ADJ_INC   AMEBA_DMA_DST_ADDR_ADJ_SET(0)

Destination address increment after each transfer.

AMEBA_DMA_DST_ADDR_ADJ_NO_CHANGE

#define AMEBA_DMA_DST_ADDR_ADJ_NO_CHANGE   AMEBA_DMA_DST_ADDR_ADJ_SET(2)

Destination address does not change.

AMEBA_DMA_DST_ADDR_ADJ_SET

#define AMEBA_DMA_DST_ADDR_ADJ_SET

(

val

)

Value:

((val & 0x3) << 4)

Set destination address adjustment bits [5:4].

Parameters

val	Address adjustment value encoded in bits [5:4].

AMEBA_DMA_DST_BURST_EIGHT

#define AMEBA_DMA_DST_BURST_EIGHT   AMEBA_DMA_DST_BURST_SET(2)

Destination burst length: 8 transfers.

AMEBA_DMA_DST_BURST_FOUR

#define AMEBA_DMA_DST_BURST_FOUR   AMEBA_DMA_DST_BURST_SET(1)

Destination burst length: 4 transfers.

AMEBA_DMA_DST_BURST_ONE

#define AMEBA_DMA_DST_BURST_ONE   AMEBA_DMA_DST_BURST_SET(0)

Destination burst length: 1 transfer.

AMEBA_DMA_DST_BURST_SET

#define AMEBA_DMA_DST_BURST_SET

(

val

)

Value:

((val & 0x1F) << 17)

Set destination burst length bits [21:17].

Parameters

val	Burst length value encoded in bits [21:17].

AMEBA_DMA_DST_BURST_SIXTEEN

#define AMEBA_DMA_DST_BURST_SIXTEEN   AMEBA_DMA_DST_BURST_SET(3)

Destination burst length: 16 transfers.

AMEBA_DMA_DST_DATA_SIZE_SET

#define AMEBA_DMA_DST_DATA_SIZE_SET

(

val

)

Value:

((val & 0x7) << 9)

Set destination data width bits [11:9].

Parameters

val	Data width value encoded in bits [11:9].

AMEBA_DMA_DST_WIDTH_16BITS

#define AMEBA_DMA_DST_WIDTH_16BITS   AMEBA_DMA_DST_DATA_SIZE_SET(1)

Destination data width: 16 bits.

AMEBA_DMA_DST_WIDTH_32BITS

#define AMEBA_DMA_DST_WIDTH_32BITS   AMEBA_DMA_DST_DATA_SIZE_SET(2)

Destination data width: 32 bits.

AMEBA_DMA_DST_WIDTH_8BITS

#define AMEBA_DMA_DST_WIDTH_8BITS   AMEBA_DMA_DST_DATA_SIZE_SET(0)

Destination data width: 8 bits.

AMEBA_DMA_MEMORY_TO_MEMORY

#define AMEBA_DMA_MEMORY_TO_MEMORY   AMEBA_DMA_CH_DIR_SET(0)

DMA transfer direction: memory to memory.

AMEBA_DMA_MEMORY_TO_PERIPH

#define AMEBA_DMA_MEMORY_TO_PERIPH   AMEBA_DMA_CH_DIR_SET(1)

DMA transfer direction: memory to peripheral.

AMEBA_DMA_PERIPH_RX

#define AMEBA_DMA_PERIPH_RX   (AMEBA_DMA_PERIPH_TO_MEMORY | AMEBA_DMA_SRC_ADDR_ADJ_NO_CHANGE | AMEBA_DMA_DST_ADDR_ADJ_INC)

Typical peripheral RX configuration.

Peripheral to memory, source address fixed, destination address increment.

AMEBA_DMA_PERIPH_TO_MEMORY

#define AMEBA_DMA_PERIPH_TO_MEMORY   AMEBA_DMA_CH_DIR_SET(2)

DMA transfer direction: peripheral to memory.

AMEBA_DMA_PERIPH_TO_PERIPH

#define AMEBA_DMA_PERIPH_TO_PERIPH   AMEBA_DMA_CH_DIR_SET(3)

DMA transfer direction: peripheral to peripheral.

AMEBA_DMA_PERIPH_TX

#define AMEBA_DMA_PERIPH_TX   (AMEBA_DMA_MEMORY_TO_PERIPH | AMEBA_DMA_SRC_ADDR_ADJ_INC | AMEBA_DMA_DST_ADDR_ADJ_NO_CHANGE)

Typical peripheral TX configuration.

Memory to peripheral, source address increment, destination address fixed.

AMEBA_DMA_SRC_ADDR_ADJ_INC

#define AMEBA_DMA_SRC_ADDR_ADJ_INC   AMEBA_DMA_SRC_ADDR_ADJ_SET(0)

Source address increment after each transfer.

AMEBA_DMA_SRC_ADDR_ADJ_NO_CHANGE

#define AMEBA_DMA_SRC_ADDR_ADJ_NO_CHANGE   AMEBA_DMA_SRC_ADDR_ADJ_SET(2)

Source address does not change.

AMEBA_DMA_SRC_ADDR_ADJ_SET

#define AMEBA_DMA_SRC_ADDR_ADJ_SET

(

val

)

Value:

((val & 0x3) << 2)

Set source address adjustment bits [3:2].

Parameters

val	Address adjustment value encoded in bits [3:2].

AMEBA_DMA_SRC_BURST_EIGHT

#define AMEBA_DMA_SRC_BURST_EIGHT   AMEBA_DMA_SRC_BURST_SET(2)

Source burst length: 8 transfers.

AMEBA_DMA_SRC_BURST_FOUR

#define AMEBA_DMA_SRC_BURST_FOUR   AMEBA_DMA_SRC_BURST_SET(1)

Source burst length: 4 transfers.

AMEBA_DMA_SRC_BURST_ONE

#define AMEBA_DMA_SRC_BURST_ONE   AMEBA_DMA_SRC_BURST_SET(0)

Source burst length: 1 transfer.

AMEBA_DMA_SRC_BURST_SET

#define AMEBA_DMA_SRC_BURST_SET

(

val

)

Value:

((val & 0x1F) << 12)

Set source burst length bits [16:12].

Parameters

val	Burst length value encoded in bits [16:12].

AMEBA_DMA_SRC_BURST_SIXTEEN

#define AMEBA_DMA_SRC_BURST_SIXTEEN   AMEBA_DMA_SRC_BURST_SET(3)

Source burst length: 16 transfers.

AMEBA_DMA_SRC_DATA_SIZE_SET

#define AMEBA_DMA_SRC_DATA_SIZE_SET

(

val

)

Value:

((val & 0x7) << 6)

Set source data width bits [8:6].

Parameters

val	Data width value encoded in bits [8:6].

AMEBA_DMA_SRC_WIDTH_16BITS

#define AMEBA_DMA_SRC_WIDTH_16BITS   AMEBA_DMA_SRC_DATA_SIZE_SET(1)

Source data width: 16 bits.

AMEBA_DMA_SRC_WIDTH_32BITS

#define AMEBA_DMA_SRC_WIDTH_32BITS   AMEBA_DMA_SRC_DATA_SIZE_SET(2)

Source data width: 32 bits.

AMEBA_DMA_SRC_WIDTH_8BITS

#define AMEBA_DMA_SRC_WIDTH_8BITS   AMEBA_DMA_SRC_DATA_SIZE_SET(0)

Source data width: 8 bits.