Zephyr Project API 4.4.99
A Scalable Open Source RTOS
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arch.h
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1/*
2 * Copyright (c) 2014 Wind River Systems, Inc.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
15
16#ifndef ZEPHYR_INCLUDE_ARCH_ARC_ARCH_H_
17#define ZEPHYR_INCLUDE_ARCH_ARC_ARCH_H_
18
19#include <zephyr/devicetree.h>
20#include <zephyr/sw_isr_table.h>
24#include "sys-io-common.h"
25
34
35#ifdef CONFIG_ARC_CONNECT
37#endif
38
39#ifdef CONFIG_ISA_ARCV2
40#include "v2/sys_io.h"
41#ifdef CONFIG_ARC_HAS_SECURE
43#endif
44#endif
45
46#if defined(CONFIG_ARC_FIRQ) && defined(CONFIG_ISA_ARCV3)
47#error "Unsupported configuration: ARC_FIRQ and ISA_ARCV3"
48#endif
49
50/*
51 * We don't allow the configuration with FIRQ enabled and only one interrupt priority level
52 * (so all interrupts are FIRQ). Such configuration isn't supported in software and it is not
53 * beneficial from the performance point of view.
54 */
55#if defined(CONFIG_ARC_FIRQ) && CONFIG_NUM_IRQ_PRIO_LEVELS < 2
56#error "Unsupported configuration: ARC_FIRQ and (NUM_IRQ_PRIO_LEVELS < 2)"
57#endif
58
59#if CONFIG_RGF_NUM_BANKS > 1 && !defined(CONFIG_ARC_FIRQ)
60#error "Unsupported configuration: (RGF_NUM_BANKS > 1) and !ARC_FIRQ"
61#endif
62
63/*
64 * It's required to have more than one interrupt priority level to use second register bank
65 * - otherwise all interrupts will use same register bank. Such configuration isn't supported in
66 * software and it is not beneficial from the performance point of view.
67 */
68#if CONFIG_RGF_NUM_BANKS > 1 && CONFIG_NUM_IRQ_PRIO_LEVELS < 2
69#error "Unsupported configuration: (RGF_NUM_BANKS > 1) and (NUM_IRQ_PRIO_LEVELS < 2)"
70#endif
71
72#if defined(CONFIG_ARC_FIRQ_STACK) && !defined(CONFIG_ARC_FIRQ)
73#error "Unsupported configuration: ARC_FIRQ_STACK and !ARC_FIRQ"
74#endif
75
76#if defined(CONFIG_ARC_FIRQ_STACK) && CONFIG_RGF_NUM_BANKS < 2
77#error "Unsupported configuration: ARC_FIRQ_STACK and (RGF_NUM_BANKS < 2)"
78#endif
79
80/* In case of ARC 2+2 secure mode enabled the firq are not supported by HW */
81#if defined(CONFIG_ARC_FIRQ) && defined(CONFIG_ARC_HAS_SECURE)
82#error "Unsupported configuration: ARC_FIRQ and ARC_HAS_SECURE"
83#endif
84
85#if defined(CONFIG_SMP) && !defined(CONFIG_MULTITHREADING)
86#error "Non-multithreading mode isn't supported on SMP targets"
87#endif
88
89/* ARC HS DMB instruction operand masks. */
90#include <zephyr/arch/arc/dmb.h>
91
92#ifndef _ASMLANGUAGE
93
94#ifdef __cplusplus
95extern "C" {
96#endif
97
98#ifdef CONFIG_64BIT
99#define ARCH_STACK_PTR_ALIGN 8
100#else
101#define ARCH_STACK_PTR_ALIGN 4
102#endif /* CONFIG_64BIT */
103
104BUILD_ASSERT(CONFIG_ISR_STACK_SIZE % ARCH_STACK_PTR_ALIGN == 0,
105 "CONFIG_ISR_STACK_SIZE must be a multiple of ARCH_STACK_PTR_ALIGN");
106
107BUILD_ASSERT(CONFIG_ARC_EXCEPTION_STACK_SIZE % ARCH_STACK_PTR_ALIGN == 0,
108 "CONFIG_ARC_EXCEPTION_STACK_SIZE must be a multiple of ARCH_STACK_PTR_ALIGN");
109
110/* Indicate, for a minimally sized MPU region, how large it must be and what
111 * its base address must be aligned to.
112 *
113 * For regions that are NOT the minimum size, this define has no semantics
114 * on ARC MPUv2 as its regions must be power of two size and aligned to their
115 * own size. On ARC MPUv4, region sizes are arbitrary and this just indicates
116 * the required size granularity.
117 */
118#ifdef CONFIG_ARC_CORE_MPU
119#if CONFIG_ARC_MPU_VER == 2
120#define Z_ARC_MPU_ALIGN 2048
121#elif (CONFIG_ARC_MPU_VER == 3) || (CONFIG_ARC_MPU_VER == 4) || \
122 (CONFIG_ARC_MPU_VER == 6) || (CONFIG_ARC_MPU_VER == 8)
123#define Z_ARC_MPU_ALIGN 32
124#else
125#error "Unsupported MPU version"
126#endif
127#endif
128
129#ifdef CONFIG_MPU_STACK_GUARD
130#define Z_ARC_STACK_GUARD_SIZE Z_ARC_MPU_ALIGN
131#else
132#define Z_ARC_STACK_GUARD_SIZE 0
133#endif
134
135/* Kernel-only stacks have the following layout if a stack guard is enabled:
136 *
137 * +------------+ <- thread.stack_obj
138 * | Guard | } Z_ARC_STACK_GUARD_SIZE
139 * +------------+ <- thread.stack_info.start
140 * | Kernel |
141 * | stack |
142 * | |
143 * +............|
144 * | TLS | } thread.stack_info.delta
145 * +------------+ <- thread.stack_info.start + thread.stack_info.size
146 */
147#ifdef CONFIG_MPU_STACK_GUARD
148#define ARCH_KERNEL_STACK_RESERVED Z_ARC_STACK_GUARD_SIZE
149#define ARCH_KERNEL_STACK_OBJ_ALIGN Z_ARC_MPU_ALIGN
150#endif
151
152#ifdef CONFIG_USERSPACE
153/* Any thread running In user mode will have full access to the region denoted
154 * by thread.stack_info.
155 *
156 * Thread-local storage is at the very highest memory locations of this area.
157 * Memory for TLS and any initial random stack pointer offset is captured
158 * in thread.stack_info.delta.
159 */
160#ifdef CONFIG_MPU_STACK_GUARD
161/* MPU guards are only supported with V3 MPU and later. In this configuration
162 * the stack object will contain the MPU guard, the privilege stack, and then
163 * the stack buffer in that order:
164 *
165 * +------------+ <- thread.stack_obj
166 * | Guard | } Z_ARC_STACK_GUARD_SIZE
167 * +------------+ <- thread.arch.priv_stack_start
168 * | Priv Stack | } CONFIG_PRIVILEGED_STACK_SIZE
169 * +------------+ <- thread.stack_info.start
170 * | Thread |
171 * | stack |
172 * | |
173 * +............|
174 * | TLS | } thread.stack_info.delta
175 * +------------+ <- thread.stack_info.start + thread.stack_info.size
176 */
177#define ARCH_THREAD_STACK_RESERVED (Z_ARC_STACK_GUARD_SIZE + \
178 CONFIG_PRIVILEGED_STACK_SIZE)
179#define ARCH_THREAD_STACK_OBJ_ALIGN(size) Z_ARC_MPU_ALIGN
180/* We need to be able to exactly cover the stack buffer with an MPU region,
181 * so round its size up to the required granularity of the MPU
182 */
183#define ARCH_THREAD_STACK_SIZE_ADJUST(size) \
184 (ROUND_UP((size), Z_ARC_MPU_ALIGN))
185BUILD_ASSERT(CONFIG_PRIVILEGED_STACK_SIZE % Z_ARC_MPU_ALIGN == 0,
186 "improper privilege stack size");
187#else /* !CONFIG_MPU_STACK_GUARD */
188/* Userspace enabled, but supervisor stack guards are not in use */
189#ifdef CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT
190/* Use defaults for everything. The privilege elevation stack is located
191 * in another area of memory generated at build time by gen_kobject_list.py
192 *
193 * +------------+ <- thread.arch.priv_stack_start
194 * | Priv Stack | } K_KERNEL_STACK_LEN(CONFIG_PRIVILEGED_STACK_SIZE)
195 * +------------+
196 *
197 * +------------+ <- thread.stack_obj = thread.stack_info.start
198 * | Thread |
199 * | stack |
200 * | |
201 * +............|
202 * | TLS | } thread.stack_info.delta
203 * +------------+ <- thread.stack_info.start + thread.stack_info.size
204 */
205#define ARCH_THREAD_STACK_SIZE_ADJUST(size) \
206 Z_POW2_CEIL(ROUND_UP((size), Z_ARC_MPU_ALIGN))
207#define ARCH_THREAD_STACK_OBJ_ALIGN(size) \
208 ARCH_THREAD_STACK_SIZE_ADJUST(size)
209#define ARCH_THREAD_STACK_RESERVED 0
210#else /* !CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT */
211/* Reserved area of the thread object just contains the privilege stack:
212 *
213 * +------------+ <- thread.stack_obj = thread.arch.priv_stack_start
214 * | Priv Stack | } CONFIG_PRIVILEGED_STACK_SIZE
215 * +------------+ <- thread.stack_info.start
216 * | Thread |
217 * | stack |
218 * | |
219 * +............|
220 * | TLS | } thread.stack_info.delta
221 * +------------+ <- thread.stack_info.start + thread.stack_info.size
222 */
223#define ARCH_THREAD_STACK_RESERVED CONFIG_PRIVILEGED_STACK_SIZE
224#define ARCH_THREAD_STACK_SIZE_ADJUST(size) \
225 (ROUND_UP((size), Z_ARC_MPU_ALIGN))
226#define ARCH_THREAD_STACK_OBJ_ALIGN(size) Z_ARC_MPU_ALIGN
227
228BUILD_ASSERT(CONFIG_PRIVILEGED_STACK_SIZE % Z_ARC_MPU_ALIGN == 0,
229 "improper privilege stack size");
230#endif /* CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT */
231#endif /* CONFIG_MPU_STACK_GUARD */
232
233#else /* !CONFIG_USERSPACE */
234
235#ifdef CONFIG_MPU_STACK_GUARD
236/* Only supported on ARC MPU V3 and higher. Reserve some memory for the stack
237 * guard. This is just a minimally-sized region at the beginning of the stack
238 * object, which is programmed to produce an exception if written to.
239 *
240 * +------------+ <- thread.stack_obj
241 * | Guard | } Z_ARC_STACK_GUARD_SIZE
242 * +------------+ <- thread.stack_info.start
243 * | Thread |
244 * | stack |
245 * | |
246 * +............|
247 * | TLS | } thread.stack_info.delta
248 * +------------+ <- thread.stack_info.start + thread.stack_info.size
249 */
250#define ARCH_THREAD_STACK_RESERVED Z_ARC_STACK_GUARD_SIZE
251#define ARCH_THREAD_STACK_OBJ_ALIGN(size) Z_ARC_MPU_ALIGN
252/* Default for ARCH_THREAD_STACK_SIZE_ADJUST */
253#else /* !CONFIG_MPU_STACK_GUARD */
254/* No stack guard, no userspace, Use defaults for everything. */
255#endif /* CONFIG_MPU_STACK_GUARD */
256#endif /* CONFIG_USERSPACE */
257
258#ifdef CONFIG_ARC_MPU
259
260/* Legacy case: retain containing extern "C" with C++ */
262
263#define K_MEM_PARTITION_P_NA_U_NA AUX_MPU_ATTR_N
264#define K_MEM_PARTITION_P_RW_U_RW (AUX_MPU_ATTR_UW | AUX_MPU_ATTR_UR | \
265 AUX_MPU_ATTR_KW | AUX_MPU_ATTR_KR)
266#define K_MEM_PARTITION_P_RW_U_RO (AUX_MPU_ATTR_UR | \
267 AUX_MPU_ATTR_KW | AUX_MPU_ATTR_KR)
268#define K_MEM_PARTITION_P_RW_U_NA (AUX_MPU_ATTR_KW | AUX_MPU_ATTR_KR)
269#define K_MEM_PARTITION_P_RO_U_RO (AUX_MPU_ATTR_UR | AUX_MPU_ATTR_KR)
270#define K_MEM_PARTITION_P_RO_U_NA (AUX_MPU_ATTR_KR)
271
272/* Execution-allowed attributes */
273#define K_MEM_PARTITION_P_RWX_U_RWX (AUX_MPU_ATTR_UW | AUX_MPU_ATTR_UR | \
274 AUX_MPU_ATTR_KW | AUX_MPU_ATTR_KR | \
275 AUX_MPU_ATTR_KE | AUX_MPU_ATTR_UE)
276#define K_MEM_PARTITION_P_RWX_U_RX (AUX_MPU_ATTR_UR | \
277 AUX_MPU_ATTR_KW | AUX_MPU_ATTR_KR | \
278 AUX_MPU_ATTR_KE | AUX_MPU_ATTR_UE)
279#define K_MEM_PARTITION_P_RX_U_RX (AUX_MPU_ATTR_UR | \
280 AUX_MPU_ATTR_KR | \
281 AUX_MPU_ATTR_KE | AUX_MPU_ATTR_UE)
282
283#define K_MEM_PARTITION_IS_WRITABLE(attr) \
284 ({ \
285 int __is_writable__; \
286 switch (attr & (AUX_MPU_ATTR_UW | AUX_MPU_ATTR_KW)) { \
287 case (AUX_MPU_ATTR_UW | AUX_MPU_ATTR_KW): \
288 case AUX_MPU_ATTR_UW: \
289 case AUX_MPU_ATTR_KW: \
290 __is_writable__ = 1; \
291 break; \
292 default: \
293 __is_writable__ = 0; \
294 break; \
295 } \
296 __is_writable__; \
297 })
298#define K_MEM_PARTITION_IS_EXECUTABLE(attr) \
299 ((attr) & (AUX_MPU_ATTR_KE | AUX_MPU_ATTR_UE))
300
301/*
302 * BUILD_ASSERT in case of MWDT is a bit more picky in performing compile-time check.
303 * For example it can't evaluate variable address at build time like GCC toolchain can do.
304 * That's why we provide custom _ARCH_MEM_PARTITION_ALIGN_CHECK implementation for MWDT toolchain
305 * with additional check for arguments availability in compile time.
306 */
307#ifdef __CCAC__
308#define IS_BUILTIN_MWDT(val) __builtin_constant_p((uintptr_t)(val))
309#if CONFIG_ARC_MPU_VER == 2 || CONFIG_ARC_MPU_VER == 3 || CONFIG_ARC_MPU_VER == 6
310#define _ARCH_MEM_PARTITION_ALIGN_CHECK(start, size) \
311 BUILD_ASSERT(IS_BUILTIN_MWDT(size) ? !((size) & ((size) - 1)) : 1, \
312 "partition size must be power of 2"); \
313 BUILD_ASSERT(IS_BUILTIN_MWDT(size) ? (size) >= Z_ARC_MPU_ALIGN : 1, \
314 "partition size must be >= mpu address alignment."); \
315 BUILD_ASSERT(IS_BUILTIN_MWDT(size) ? IS_BUILTIN_MWDT(start) ? \
316 !((uintptr_t)(start) & ((size) - 1)) : 1 : 1, \
317 "partition start address must align with size.")
318#elif CONFIG_ARC_MPU_VER == 4 || CONFIG_ARC_MPU_VER == 8
319#define _ARCH_MEM_PARTITION_ALIGN_CHECK(start, size) \
320 BUILD_ASSERT(IS_BUILTIN_MWDT(size) ? (size) % Z_ARC_MPU_ALIGN == 0 : 1, \
321 "partition size must align with " STRINGIFY(Z_ARC_MPU_ALIGN)); \
322 BUILD_ASSERT(IS_BUILTIN_MWDT(size) ? (size) >= Z_ARC_MPU_ALIGN : 1, \
323 "partition size must be >= " STRINGIFY(Z_ARC_MPU_ALIGN)); \
324 BUILD_ASSERT(IS_BUILTIN_MWDT(start) ? (uintptr_t)(start) % Z_ARC_MPU_ALIGN == 0 : 1, \
325 "partition start address must align with " STRINGIFY(Z_ARC_MPU_ALIGN))
326#endif
327#else /* __CCAC__ */
328#if CONFIG_ARC_MPU_VER == 2 || CONFIG_ARC_MPU_VER == 3 || CONFIG_ARC_MPU_VER == 6
329#define _ARCH_MEM_PARTITION_ALIGN_CHECK(start, size) \
330 BUILD_ASSERT(!((size) & ((size) - 1)), \
331 "partition size must be power of 2"); \
332 BUILD_ASSERT((size) >= Z_ARC_MPU_ALIGN, \
333 "partition size must be >= mpu address alignment."); \
334 BUILD_ASSERT(!((uintptr_t)(start) & ((size) - 1)), \
335 "partition start address must align with size.")
336#elif CONFIG_ARC_MPU_VER == 4 || CONFIG_ARC_MPU_VER == 8
337#define _ARCH_MEM_PARTITION_ALIGN_CHECK(start, size) \
338 BUILD_ASSERT((size) % Z_ARC_MPU_ALIGN == 0, \
339 "partition size must align with " STRINGIFY(Z_ARC_MPU_ALIGN)); \
340 BUILD_ASSERT((size) >= Z_ARC_MPU_ALIGN, \
341 "partition size must be >= " STRINGIFY(Z_ARC_MPU_ALIGN)); \
342 BUILD_ASSERT((uintptr_t)(start) % Z_ARC_MPU_ALIGN == 0, \
343 "partition start address must align with " STRINGIFY(Z_ARC_MPU_ALIGN))
344#endif
345#endif /* __CCAC__ */
346#endif /* CONFIG_ARC_MPU*/
347
348/* Typedef for the k_mem_partition attribute*/
350
351static ALWAYS_INLINE void arch_nop(void)
352{
353 __builtin_arc_nop();
354}
355
356#ifndef CONFIG_XIP
357extern char __arc_rw_sram_size[];
358#endif /* CONFIG_XIP */
359
360#endif /* _ASMLANGUAGE */
361
362#ifdef __cplusplus
363}
364#endif
365#endif /* ZEPHYR_INCLUDE_ARCH_ARC_ARCH_H_ */
static ALWAYS_INLINE void arch_nop(void)
Definition arch.h:351
#define ARCH_STACK_PTR_ALIGN
Definition arch.h:101
ARCv2 public kernel miscellaneous.
ARCv2 ARC Connect driver.
Per-arch thread definition.
ARCv2 public interrupt handling.
ARCv2 auxiliary registers definitions.
Devicetree main header.
Copyright (c) 2026 GlobalFoundries Inc.
ARCv2 public error handling.
#define ALWAYS_INLINE
Definition common.h:180
#define BUILD_ASSERT(EXPR, MSG...)
Definition llvm.h:51
__UINT32_TYPE__ uint32_t
Definition stdint.h:90
Definition arm_mpu_v7m.h:155
Software-managed ISR table.