Zephyr Project API 3.7.0
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arc_connect.h File Reference

ARCv2 ARC Connect driver. More...

Go to the source code of this file.

Data Structures

struct  arc_connect_cmd
 
struct  arc_connect_bcr
 
struct  arc_connect_idu_bcr
 

Macros

#define ARC_CONNECT_CMD_CHECK_CORE_ID   0x0
 
#define ARC_CONNECT_CMD_INTRPT_GENERATE_IRQ   0x1
 
#define ARC_CONNECT_CMD_INTRPT_GENERATE_ACK   0x2
 
#define ARC_CONNECT_CMD_INTRPT_READ_STATUS   0x3
 
#define ARC_CONNECT_CMD_INTRPT_CHECK_SOURCE   0x4
 
#define ARC_CONNECT_CMD_SEMA_CLAIM_AND_READ   0x11
 
#define ARC_CONNECT_CMD_SEMA_RELEASE   0x12
 
#define ARC_CONNECT_CMD_SEMA_FORCE_RELEASE   0x13
 
#define ARC_CONNECT_CMD_MSG_SRAM_SET_ADDR   0x21
 
#define ARC_CONNECT_CMD_MSG_SRAM_READ_ADDR   0x22
 
#define ARC_CONNECT_CMD_MSG_SRAM_SET_ADDR_OFFSET   0x23
 
#define ARC_CONNECT_CMD_MSG_SRAM_READ_ADDR_OFFSET   0x24
 
#define ARC_CONNECT_CMD_MSG_SRAM_WRITE   0x25
 
#define ARC_CONNECT_CMD_MSG_SRAM_WRITE_INC   0x26
 
#define ARC_CONNECT_CMD_MSG_SRAM_WRITE_IMM   0x27
 
#define ARC_CONNECT_CMD_MSG_SRAM_READ   0x28
 
#define ARC_CONNECT_CMD_MSG_SRAM_READ_INC   0x29
 
#define ARC_CONNECT_CMD_MSG_SRAM_READ_IMM   0x2a
 
#define ARC_CONNECT_CMD_MSG_SRAM_SET_ECC_CTRL   0x2b
 
#define ARC_CONNECT_CMD_MSG_SRAM_READ_ECC_CTRL   0x2c
 
#define ARC_CONNECT_CMD_DEBUG_RESET   0x31
 
#define ARC_CONNECT_CMD_DEBUG_HALT   0x32
 
#define ARC_CONNECT_CMD_DEBUG_RUN   0x33
 
#define ARC_CONNECT_CMD_DEBUG_SET_MASK   0x34
 
#define ARC_CONNECT_CMD_DEBUG_READ_MASK   0x35
 
#define ARC_CONNECT_CMD_DEBUG_SET_SELECT   0x36
 
#define ARC_CONNECT_CMD_DEBUG_READ_SELECT   0x37
 
#define ARC_CONNECT_CMD_DEBUG_READ_EN   0x38
 
#define ARC_CONNECT_CMD_DEBUG_READ_CMD   0x39
 
#define ARC_CONNECT_CMD_DEBUG_READ_CORE   0x3a
 
#define ARC_CONNECT_CMD_DEBUG_MASK_SH   0x08 /* if a self-halt occurs, a global halt is triggered */
 
#define ARC_CONNECT_CMD_DEBUG_MASK_BH   0x04 /* if a breakpoint caused halt occurs, a global halt is triggered */
 
#define ARC_CONNECT_CMD_DEBUG_MASK_AH   0x02 /* if an actionpoint caused halt occurs, a global halt is triggered */
 
#define ARC_CONNECT_CMD_DEBUG_MASK_H   0x01 /* whenever the core is halted, a global halt is triggered */
 
#define ARC_CONNECT_CMD_GFRC_CLEAR   0x41
 
#define ARC_CONNECT_CMD_GFRC_READ_LO   0x42
 
#define ARC_CONNECT_CMD_GFRC_READ_HI   0x43
 
#define ARC_CONNECT_CMD_GFRC_ENABLE   0x44
 
#define ARC_CONNECT_CMD_GFRC_DISABLE   0x45
 
#define ARC_CONNECT_CMD_GFRC_READ_DISABLE   0x46
 
#define ARC_CONNECT_CMD_GFRC_SET_CORE   0x47
 
#define ARC_CONNECT_CMD_GFRC_READ_CORE   0x48
 
#define ARC_CONNECT_CMD_GFRC_READ_HALT   0x49
 
#define ARC_CONNECT_CMD_PDM_SET_PM   0x81
 
#define ARC_CONNECT_CMD_PDM_READ_PSTATUS   0x82
 
#define ARC_CONNECT_CMD_PMU_SET_PUCNT   0x51
 
#define ARC_CONNECT_CMD_PMU_READ_PUCNT   0x52
 
#define ARC_CONNECT_CMD_PMU_SET_RSTCNT   0x53
 
#define ARC_CONNECT_CMD_PMU_READ_RSTCNT   0x54
 
#define ARC_CONNECT_CMD_PMU_SET_PDCNT   0x55
 
#define ARC_CONNECT_CMD_PMU_READ_PDCNT   0x56
 
#define ARC_CONNECT_CMD_IDU_ENABLE   0x71
 
#define ARC_CONNECT_CMD_IDU_DISABLE   0x72
 
#define ARC_CONNECT_CMD_IDU_READ_ENABLE   0x73
 
#define ARC_CONNECT_CMD_IDU_SET_MODE   0x74
 
#define ARC_CONNECT_CMD_IDU_READ_MODE   0x75
 
#define ARC_CONNECT_CMD_IDU_SET_DEST   0x76
 
#define ARC_CONNECT_CMD_IDU_READ_DEST   0x77
 
#define ARC_CONNECT_CMD_IDU_GEN_CIRQ   0x78
 
#define ARC_CONNECT_CMD_IDU_ACK_CIRQ   0x79
 
#define ARC_CONNECT_CMD_IDU_CHECK_STATUS   0x7a
 
#define ARC_CONNECT_CMD_IDU_CHECK_SOURCE   0x7b
 
#define ARC_CONNECT_CMD_IDU_SET_MASK   0x7c
 
#define ARC_CONNECT_CMD_IDU_READ_MASK   0x7d
 
#define ARC_CONNECT_CMD_IDU_CHECK_FIRST   0x7e
 
#define ARC_CONNECT_IDU_IRQ_START   24
 
#define ARC_CONNECT_INTRPT_TRIGGER_LEVEL   0
 
#define ARC_CONNECT_INTRPT_TRIGGER_EDGE   1
 
#define ARC_CONNECT_DISTRI_MODE_ROUND_ROBIN   0
 
#define ARC_CONNECT_DISTRI_MODE_FIRST_ACK   1
 
#define ARC_CONNECT_DISTRI_ALL_DEST   2
 

Detailed Description

ARCv2 ARC Connect driver.

ARCv2 ARC Connect driver interface. Included by arc/arch.h.

Macro Definition Documentation

◆ ARC_CONNECT_CMD_CHECK_CORE_ID

#define ARC_CONNECT_CMD_CHECK_CORE_ID   0x0

◆ ARC_CONNECT_CMD_DEBUG_HALT

#define ARC_CONNECT_CMD_DEBUG_HALT   0x32

◆ ARC_CONNECT_CMD_DEBUG_MASK_AH

#define ARC_CONNECT_CMD_DEBUG_MASK_AH   0x02 /* if an actionpoint caused halt occurs, a global halt is triggered */

◆ ARC_CONNECT_CMD_DEBUG_MASK_BH

#define ARC_CONNECT_CMD_DEBUG_MASK_BH   0x04 /* if a breakpoint caused halt occurs, a global halt is triggered */

◆ ARC_CONNECT_CMD_DEBUG_MASK_H

#define ARC_CONNECT_CMD_DEBUG_MASK_H   0x01 /* whenever the core is halted, a global halt is triggered */

◆ ARC_CONNECT_CMD_DEBUG_MASK_SH

#define ARC_CONNECT_CMD_DEBUG_MASK_SH   0x08 /* if a self-halt occurs, a global halt is triggered */

◆ ARC_CONNECT_CMD_DEBUG_READ_CMD

#define ARC_CONNECT_CMD_DEBUG_READ_CMD   0x39

◆ ARC_CONNECT_CMD_DEBUG_READ_CORE

#define ARC_CONNECT_CMD_DEBUG_READ_CORE   0x3a

◆ ARC_CONNECT_CMD_DEBUG_READ_EN

#define ARC_CONNECT_CMD_DEBUG_READ_EN   0x38

◆ ARC_CONNECT_CMD_DEBUG_READ_MASK

#define ARC_CONNECT_CMD_DEBUG_READ_MASK   0x35

◆ ARC_CONNECT_CMD_DEBUG_READ_SELECT

#define ARC_CONNECT_CMD_DEBUG_READ_SELECT   0x37

◆ ARC_CONNECT_CMD_DEBUG_RESET

#define ARC_CONNECT_CMD_DEBUG_RESET   0x31

◆ ARC_CONNECT_CMD_DEBUG_RUN

#define ARC_CONNECT_CMD_DEBUG_RUN   0x33

◆ ARC_CONNECT_CMD_DEBUG_SET_MASK

#define ARC_CONNECT_CMD_DEBUG_SET_MASK   0x34

◆ ARC_CONNECT_CMD_DEBUG_SET_SELECT

#define ARC_CONNECT_CMD_DEBUG_SET_SELECT   0x36

◆ ARC_CONNECT_CMD_GFRC_CLEAR

#define ARC_CONNECT_CMD_GFRC_CLEAR   0x41

◆ ARC_CONNECT_CMD_GFRC_DISABLE

#define ARC_CONNECT_CMD_GFRC_DISABLE   0x45

◆ ARC_CONNECT_CMD_GFRC_ENABLE

#define ARC_CONNECT_CMD_GFRC_ENABLE   0x44

◆ ARC_CONNECT_CMD_GFRC_READ_CORE

#define ARC_CONNECT_CMD_GFRC_READ_CORE   0x48

◆ ARC_CONNECT_CMD_GFRC_READ_DISABLE

#define ARC_CONNECT_CMD_GFRC_READ_DISABLE   0x46

◆ ARC_CONNECT_CMD_GFRC_READ_HALT

#define ARC_CONNECT_CMD_GFRC_READ_HALT   0x49

◆ ARC_CONNECT_CMD_GFRC_READ_HI

#define ARC_CONNECT_CMD_GFRC_READ_HI   0x43

◆ ARC_CONNECT_CMD_GFRC_READ_LO

#define ARC_CONNECT_CMD_GFRC_READ_LO   0x42

◆ ARC_CONNECT_CMD_GFRC_SET_CORE

#define ARC_CONNECT_CMD_GFRC_SET_CORE   0x47

◆ ARC_CONNECT_CMD_IDU_ACK_CIRQ

#define ARC_CONNECT_CMD_IDU_ACK_CIRQ   0x79

◆ ARC_CONNECT_CMD_IDU_CHECK_FIRST

#define ARC_CONNECT_CMD_IDU_CHECK_FIRST   0x7e

◆ ARC_CONNECT_CMD_IDU_CHECK_SOURCE

#define ARC_CONNECT_CMD_IDU_CHECK_SOURCE   0x7b

◆ ARC_CONNECT_CMD_IDU_CHECK_STATUS

#define ARC_CONNECT_CMD_IDU_CHECK_STATUS   0x7a

◆ ARC_CONNECT_CMD_IDU_DISABLE

#define ARC_CONNECT_CMD_IDU_DISABLE   0x72

◆ ARC_CONNECT_CMD_IDU_ENABLE

#define ARC_CONNECT_CMD_IDU_ENABLE   0x71

◆ ARC_CONNECT_CMD_IDU_GEN_CIRQ

#define ARC_CONNECT_CMD_IDU_GEN_CIRQ   0x78

◆ ARC_CONNECT_CMD_IDU_READ_DEST

#define ARC_CONNECT_CMD_IDU_READ_DEST   0x77

◆ ARC_CONNECT_CMD_IDU_READ_ENABLE

#define ARC_CONNECT_CMD_IDU_READ_ENABLE   0x73

◆ ARC_CONNECT_CMD_IDU_READ_MASK

#define ARC_CONNECT_CMD_IDU_READ_MASK   0x7d

◆ ARC_CONNECT_CMD_IDU_READ_MODE

#define ARC_CONNECT_CMD_IDU_READ_MODE   0x75

◆ ARC_CONNECT_CMD_IDU_SET_DEST

#define ARC_CONNECT_CMD_IDU_SET_DEST   0x76

◆ ARC_CONNECT_CMD_IDU_SET_MASK

#define ARC_CONNECT_CMD_IDU_SET_MASK   0x7c

◆ ARC_CONNECT_CMD_IDU_SET_MODE

#define ARC_CONNECT_CMD_IDU_SET_MODE   0x74

◆ ARC_CONNECT_CMD_INTRPT_CHECK_SOURCE

#define ARC_CONNECT_CMD_INTRPT_CHECK_SOURCE   0x4

◆ ARC_CONNECT_CMD_INTRPT_GENERATE_ACK

#define ARC_CONNECT_CMD_INTRPT_GENERATE_ACK   0x2

◆ ARC_CONNECT_CMD_INTRPT_GENERATE_IRQ

#define ARC_CONNECT_CMD_INTRPT_GENERATE_IRQ   0x1

◆ ARC_CONNECT_CMD_INTRPT_READ_STATUS

#define ARC_CONNECT_CMD_INTRPT_READ_STATUS   0x3

◆ ARC_CONNECT_CMD_MSG_SRAM_READ

#define ARC_CONNECT_CMD_MSG_SRAM_READ   0x28

◆ ARC_CONNECT_CMD_MSG_SRAM_READ_ADDR

#define ARC_CONNECT_CMD_MSG_SRAM_READ_ADDR   0x22

◆ ARC_CONNECT_CMD_MSG_SRAM_READ_ADDR_OFFSET

#define ARC_CONNECT_CMD_MSG_SRAM_READ_ADDR_OFFSET   0x24

◆ ARC_CONNECT_CMD_MSG_SRAM_READ_ECC_CTRL

#define ARC_CONNECT_CMD_MSG_SRAM_READ_ECC_CTRL   0x2c

◆ ARC_CONNECT_CMD_MSG_SRAM_READ_IMM

#define ARC_CONNECT_CMD_MSG_SRAM_READ_IMM   0x2a

◆ ARC_CONNECT_CMD_MSG_SRAM_READ_INC

#define ARC_CONNECT_CMD_MSG_SRAM_READ_INC   0x29

◆ ARC_CONNECT_CMD_MSG_SRAM_SET_ADDR

#define ARC_CONNECT_CMD_MSG_SRAM_SET_ADDR   0x21

◆ ARC_CONNECT_CMD_MSG_SRAM_SET_ADDR_OFFSET

#define ARC_CONNECT_CMD_MSG_SRAM_SET_ADDR_OFFSET   0x23

◆ ARC_CONNECT_CMD_MSG_SRAM_SET_ECC_CTRL

#define ARC_CONNECT_CMD_MSG_SRAM_SET_ECC_CTRL   0x2b

◆ ARC_CONNECT_CMD_MSG_SRAM_WRITE

#define ARC_CONNECT_CMD_MSG_SRAM_WRITE   0x25

◆ ARC_CONNECT_CMD_MSG_SRAM_WRITE_IMM

#define ARC_CONNECT_CMD_MSG_SRAM_WRITE_IMM   0x27

◆ ARC_CONNECT_CMD_MSG_SRAM_WRITE_INC

#define ARC_CONNECT_CMD_MSG_SRAM_WRITE_INC   0x26

◆ ARC_CONNECT_CMD_PDM_READ_PSTATUS

#define ARC_CONNECT_CMD_PDM_READ_PSTATUS   0x82

◆ ARC_CONNECT_CMD_PDM_SET_PM

#define ARC_CONNECT_CMD_PDM_SET_PM   0x81

◆ ARC_CONNECT_CMD_PMU_READ_PDCNT

#define ARC_CONNECT_CMD_PMU_READ_PDCNT   0x56

◆ ARC_CONNECT_CMD_PMU_READ_PUCNT

#define ARC_CONNECT_CMD_PMU_READ_PUCNT   0x52

◆ ARC_CONNECT_CMD_PMU_READ_RSTCNT

#define ARC_CONNECT_CMD_PMU_READ_RSTCNT   0x54

◆ ARC_CONNECT_CMD_PMU_SET_PDCNT

#define ARC_CONNECT_CMD_PMU_SET_PDCNT   0x55

◆ ARC_CONNECT_CMD_PMU_SET_PUCNT

#define ARC_CONNECT_CMD_PMU_SET_PUCNT   0x51

◆ ARC_CONNECT_CMD_PMU_SET_RSTCNT

#define ARC_CONNECT_CMD_PMU_SET_RSTCNT   0x53

◆ ARC_CONNECT_CMD_SEMA_CLAIM_AND_READ

#define ARC_CONNECT_CMD_SEMA_CLAIM_AND_READ   0x11

◆ ARC_CONNECT_CMD_SEMA_FORCE_RELEASE

#define ARC_CONNECT_CMD_SEMA_FORCE_RELEASE   0x13

◆ ARC_CONNECT_CMD_SEMA_RELEASE

#define ARC_CONNECT_CMD_SEMA_RELEASE   0x12

◆ ARC_CONNECT_DISTRI_ALL_DEST

#define ARC_CONNECT_DISTRI_ALL_DEST   2

◆ ARC_CONNECT_DISTRI_MODE_FIRST_ACK

#define ARC_CONNECT_DISTRI_MODE_FIRST_ACK   1

◆ ARC_CONNECT_DISTRI_MODE_ROUND_ROBIN

#define ARC_CONNECT_DISTRI_MODE_ROUND_ROBIN   0

◆ ARC_CONNECT_IDU_IRQ_START

#define ARC_CONNECT_IDU_IRQ_START   24

◆ ARC_CONNECT_INTRPT_TRIGGER_EDGE

#define ARC_CONNECT_INTRPT_TRIGGER_EDGE   1

◆ ARC_CONNECT_INTRPT_TRIGGER_LEVEL

#define ARC_CONNECT_INTRPT_TRIGGER_LEVEL   0