Zephyr Project API 3.7.0
A Scalable Open Source RTOS
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arc_connect.h
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1/*
2 * Copyright (c) 2019 Synopsys.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
14#ifndef ZEPHYR_INCLUDE_ARCH_ARC_V2_ARC_CONNECT_H_
15#define ZEPHYR_INCLUDE_ARCH_ARC_V2_ARC_CONNECT_H_
16
17#ifndef _ASMLANGUAGE
18#include <zephyr/types.h>
20
21#ifdef __cplusplus
22extern "C" {
23#endif
24
25#define _ARC_V2_CONNECT_BCR 0x0d0
26#define _ARC_V2_CONNECT_IDU_BCR 0x0d5
27#define _ARC_V2_CONNECT_GFRC_BCR 0x0d6
28#define _ARC_V2_CONNECT_CMD 0x600
29#define _ARC_V2_CONNECT_WDATA 0x601
30#define _ARC_V2_CONNECT_READBACK 0x602
31
32
33#define ARC_CONNECT_CMD_CHECK_CORE_ID 0x0
34
35#define ARC_CONNECT_CMD_INTRPT_GENERATE_IRQ 0x1
36#define ARC_CONNECT_CMD_INTRPT_GENERATE_ACK 0x2
37#define ARC_CONNECT_CMD_INTRPT_READ_STATUS 0x3
38#define ARC_CONNECT_CMD_INTRPT_CHECK_SOURCE 0x4
39
40#define ARC_CONNECT_CMD_SEMA_CLAIM_AND_READ 0x11
41#define ARC_CONNECT_CMD_SEMA_RELEASE 0x12
42#define ARC_CONNECT_CMD_SEMA_FORCE_RELEASE 0x13
43
44#define ARC_CONNECT_CMD_MSG_SRAM_SET_ADDR 0x21
45#define ARC_CONNECT_CMD_MSG_SRAM_READ_ADDR 0x22
46#define ARC_CONNECT_CMD_MSG_SRAM_SET_ADDR_OFFSET 0x23
47#define ARC_CONNECT_CMD_MSG_SRAM_READ_ADDR_OFFSET 0x24
48#define ARC_CONNECT_CMD_MSG_SRAM_WRITE 0x25
49#define ARC_CONNECT_CMD_MSG_SRAM_WRITE_INC 0x26
50#define ARC_CONNECT_CMD_MSG_SRAM_WRITE_IMM 0x27
51#define ARC_CONNECT_CMD_MSG_SRAM_READ 0x28
52#define ARC_CONNECT_CMD_MSG_SRAM_READ_INC 0x29
53#define ARC_CONNECT_CMD_MSG_SRAM_READ_IMM 0x2a
54#define ARC_CONNECT_CMD_MSG_SRAM_SET_ECC_CTRL 0x2b
55#define ARC_CONNECT_CMD_MSG_SRAM_READ_ECC_CTRL 0x2c
56
57#define ARC_CONNECT_CMD_DEBUG_RESET 0x31
58#define ARC_CONNECT_CMD_DEBUG_HALT 0x32
59#define ARC_CONNECT_CMD_DEBUG_RUN 0x33
60#define ARC_CONNECT_CMD_DEBUG_SET_MASK 0x34
61#define ARC_CONNECT_CMD_DEBUG_READ_MASK 0x35
62#define ARC_CONNECT_CMD_DEBUG_SET_SELECT 0x36
63#define ARC_CONNECT_CMD_DEBUG_READ_SELECT 0x37
64#define ARC_CONNECT_CMD_DEBUG_READ_EN 0x38
65#define ARC_CONNECT_CMD_DEBUG_READ_CMD 0x39
66#define ARC_CONNECT_CMD_DEBUG_READ_CORE 0x3a
67
68#define ARC_CONNECT_CMD_DEBUG_MASK_SH 0x08 /* if a self-halt occurs, a global halt is triggered */
69#define ARC_CONNECT_CMD_DEBUG_MASK_BH 0x04 /* if a breakpoint caused halt occurs, a global halt is triggered */
70#define ARC_CONNECT_CMD_DEBUG_MASK_AH 0x02 /* if an actionpoint caused halt occurs, a global halt is triggered */
71#define ARC_CONNECT_CMD_DEBUG_MASK_H 0x01 /* whenever the core is halted, a global halt is triggered */
72
73#define ARC_CONNECT_CMD_GFRC_CLEAR 0x41
74#define ARC_CONNECT_CMD_GFRC_READ_LO 0x42
75#define ARC_CONNECT_CMD_GFRC_READ_HI 0x43
76#define ARC_CONNECT_CMD_GFRC_ENABLE 0x44
77#define ARC_CONNECT_CMD_GFRC_DISABLE 0x45
78#define ARC_CONNECT_CMD_GFRC_READ_DISABLE 0x46
79#define ARC_CONNECT_CMD_GFRC_SET_CORE 0x47
80#define ARC_CONNECT_CMD_GFRC_READ_CORE 0x48
81#define ARC_CONNECT_CMD_GFRC_READ_HALT 0x49
82
83#define ARC_CONNECT_CMD_PDM_SET_PM 0x81
84#define ARC_CONNECT_CMD_PDM_READ_PSTATUS 0x82
85
86#define ARC_CONNECT_CMD_PMU_SET_PUCNT 0x51
87#define ARC_CONNECT_CMD_PMU_READ_PUCNT 0x52
88#define ARC_CONNECT_CMD_PMU_SET_RSTCNT 0x53
89#define ARC_CONNECT_CMD_PMU_READ_RSTCNT 0x54
90#define ARC_CONNECT_CMD_PMU_SET_PDCNT 0x55
91#define ARC_CONNECT_CMD_PMU_READ_PDCNT 0x56
92
93#define ARC_CONNECT_CMD_IDU_ENABLE 0x71
94#define ARC_CONNECT_CMD_IDU_DISABLE 0x72
95#define ARC_CONNECT_CMD_IDU_READ_ENABLE 0x73
96#define ARC_CONNECT_CMD_IDU_SET_MODE 0x74
97#define ARC_CONNECT_CMD_IDU_READ_MODE 0x75
98#define ARC_CONNECT_CMD_IDU_SET_DEST 0x76
99#define ARC_CONNECT_CMD_IDU_READ_DEST 0x77
100#define ARC_CONNECT_CMD_IDU_GEN_CIRQ 0x78
101#define ARC_CONNECT_CMD_IDU_ACK_CIRQ 0x79
102#define ARC_CONNECT_CMD_IDU_CHECK_STATUS 0x7a
103#define ARC_CONNECT_CMD_IDU_CHECK_SOURCE 0x7b
104#define ARC_CONNECT_CMD_IDU_SET_MASK 0x7c
105#define ARC_CONNECT_CMD_IDU_READ_MASK 0x7d
106#define ARC_CONNECT_CMD_IDU_CHECK_FIRST 0x7e
107
108/* the start intno of common interrupt managed by IDU */
109#define ARC_CONNECT_IDU_IRQ_START 24
110
111#define ARC_CONNECT_INTRPT_TRIGGER_LEVEL 0
112#define ARC_CONNECT_INTRPT_TRIGGER_EDGE 1
113
114
115#define ARC_CONNECT_DISTRI_MODE_ROUND_ROBIN 0
116#define ARC_CONNECT_DISTRI_MODE_FIRST_ACK 1
117#define ARC_CONNECT_DISTRI_ALL_DEST 2
118
120 union {
121 struct {
122#ifdef CONFIG_BIG_ENDIAN
123 uint32_t pad:8, param:16, cmd:8;
124#else
126#endif
127 };
129 };
130};
131
133 union {
134 struct {
135#ifdef CONFIG_BIG_ENDIAN
136 uint32_t pad4:6, pw_dom:1, pad3:1,
137 idu:1, pad2:1, num_cores:6,
138 pad:1, gfrc:1, dbg:1, pw:1,
139 msg:1, sem:1, ipi:1, slv:1,
140 ver:8;
141#else
143 slv:1, ipi:1, sem:1, msg:1,
144 pw:1, dbg:1, gfrc:1, pad:1,
146 pad3:1, pw_dom:1, pad4:6;
147#endif
148 };
150 };
151};
152
154 union {
155 struct {
156#ifdef CONFIG_BIG_ENDIAN
157 uint32_t pad:21, cirqnum:3, ver:8;
158#else
160#endif
161 };
163 };
164};
165
166static inline void z_arc_connect_cmd(uint32_t cmd, uint32_t param)
167{
168 struct arc_connect_cmd regval;
169
170 regval.pad = 0;
171 regval.cmd = cmd;
172 regval.param = param;
173
174 z_arc_v2_aux_reg_write(_ARC_V2_CONNECT_CMD, regval.val);
175}
176
177static inline void z_arc_connect_cmd_data(uint32_t cmd, uint32_t param,
179{
180 z_arc_v2_aux_reg_write(_ARC_V2_CONNECT_WDATA, data);
181 z_arc_connect_cmd(cmd, param);
182}
183
184static inline uint32_t z_arc_connect_cmd_readback(void)
185{
186 return z_arc_v2_aux_reg_read(_ARC_V2_CONNECT_READBACK);
187}
188
189
190/* inter-core interrupt related functions */
191extern void z_arc_connect_ici_generate(uint32_t core_id);
192extern void z_arc_connect_ici_ack(uint32_t core_id);
193extern uint32_t z_arc_connect_ici_read_status(uint32_t core_id);
194extern uint32_t z_arc_connect_ici_check_src(void);
195extern void z_arc_connect_ici_clear(void);
196
197/* inter-core debug related functions */
198extern void z_arc_connect_debug_reset(uint32_t core_mask);
199extern void z_arc_connect_debug_halt(uint32_t core_mask);
200extern void z_arc_connect_debug_run(uint32_t core_mask);
201extern void z_arc_connect_debug_mask_set(uint32_t core_mask, uint32_t mask);
202extern uint32_t z_arc_connect_debug_mask_read(uint32_t core_mask);
203extern void z_arc_connect_debug_select_set(uint32_t core_mask);
204extern uint32_t z_arc_connect_debug_select_read(void);
205extern uint32_t z_arc_connect_debug_en_read(void);
206extern uint32_t z_arc_connect_debug_cmd_read(void);
207extern uint32_t z_arc_connect_debug_core_read(void);
208
209/* global free-running counter(gfrc) related functions */
210extern void z_arc_connect_gfrc_clear(void);
211extern uint64_t z_arc_connect_gfrc_read(void);
212extern void z_arc_connect_gfrc_enable(void);
213extern void z_arc_connect_gfrc_disable(void);
214extern void z_arc_connect_gfrc_core_set(uint32_t core_mask);
215extern uint32_t z_arc_connect_gfrc_halt_read(void);
216extern uint32_t z_arc_connect_gfrc_core_read(void);
217
218/* interrupt distribute unit related functions */
219extern void z_arc_connect_idu_enable(void);
220extern void z_arc_connect_idu_disable(void);
221extern uint32_t z_arc_connect_idu_read_enable(void);
222extern void z_arc_connect_idu_set_mode(uint32_t irq_num,
223 uint16_t trigger_mode, uint16_t distri_mode);
224extern uint32_t z_arc_connect_idu_read_mode(uint32_t irq_num);
225extern void z_arc_connect_idu_set_dest(uint32_t irq_num, uint32_t core_mask);
226extern uint32_t z_arc_connect_idu_read_dest(uint32_t irq_num);
227extern void z_arc_connect_idu_gen_cirq(uint32_t irq_num);
228extern void z_arc_connect_idu_ack_cirq(uint32_t irq_num);
229extern uint32_t z_arc_connect_idu_check_status(uint32_t irq_num);
230extern uint32_t z_arc_connect_idu_check_source(uint32_t irq_num);
231extern void z_arc_connect_idu_set_mask(uint32_t irq_num, uint32_t mask);
232extern uint32_t z_arc_connect_idu_read_mask(uint32_t irq_num);
233extern uint32_t z_arc_connect_idu_check_first(uint32_t irq_num);
234
235#ifdef __cplusplus
236}
237#endif
238
239#endif /* _ASMLANGUAGE */
240
241#endif /* ZEPHYR_INCLUDE_ARCH_ARC_V2_ARC_CONNECT_H_ */
ARCv2 auxiliary registers definitions.
static void cmd(uint32_t command)
Execute a display list command by co-processor engine.
Definition ft8xx_reference_api.h:153
__UINT32_TYPE__ uint32_t
Definition stdint.h:90
__UINT64_TYPE__ uint64_t
Definition stdint.h:91
__UINT16_TYPE__ uint16_t
Definition stdint.h:89
Definition arc_connect.h:132
uint32_t pw
Definition arc_connect.h:144
uint32_t val
Definition arc_connect.h:149
uint32_t idu
Definition arc_connect.h:145
uint32_t gfrc
Definition arc_connect.h:144
uint32_t num_cores
Definition arc_connect.h:145
uint32_t slv
Definition arc_connect.h:143
uint32_t ipi
Definition arc_connect.h:143
uint32_t pw_dom
Definition arc_connect.h:146
uint32_t pad2
Definition arc_connect.h:145
uint32_t pad
Definition arc_connect.h:144
uint32_t msg
Definition arc_connect.h:143
uint32_t pad4
Definition arc_connect.h:146
uint32_t pad3
Definition arc_connect.h:146
uint32_t ver
Definition arc_connect.h:142
uint32_t sem
Definition arc_connect.h:143
uint32_t dbg
Definition arc_connect.h:144
Definition arc_connect.h:119
uint32_t param
Definition arc_connect.h:125
uint32_t cmd
Definition arc_connect.h:125
uint32_t val
Definition arc_connect.h:128
uint32_t pad
Definition arc_connect.h:125
Definition arc_connect.h:153
uint32_t pad
Definition arc_connect.h:159
uint32_t val
Definition arc_connect.h:162
uint32_t cirqnum
Definition arc_connect.h:159
uint32_t ver
Definition arc_connect.h:159
static fdata_t data[2]
Definition test_fifo_contexts.c:15