cache.h File Reference

#include <zephyr/types.h>
#include <zephyr/sys/util.h>
#include <zephyr/sys/barrier.h>
#include <zephyr/arch/cpu.h>
#include <errno.h>

Go to the source code of this file.

Macros
#define	K_CACHE_WB   BIT(0)
#define	K_CACHE_INVD   BIT(1)
#define	K_CACHE_WB_INVD   (K_CACHE_WB | K_CACHE_INVD)
#define	CTR_EL0_DMINLINE_SHIFT   16
#define	CTR_EL0_DMINLINE_MASK   BIT_MASK(4)
#define	CTR_EL0_CWG_SHIFT   24
#define	CTR_EL0_CWG_MASK   BIT_MASK(4)
#define	CLIDR_EL1_LOC_SHIFT   24
#define	CLIDR_EL1_LOC_MASK   BIT_MASK(3)
#define	CLIDR_EL1_CTYPE_SHIFT(level)
#define	CLIDR_EL1_CTYPE_MASK   BIT_MASK(3)
#define	CCSIDR_EL1_LN_SZ_SHIFT   0
#define	CCSIDR_EL1_LN_SZ_MASK   BIT_MASK(3)
#define	CCSIDR_EL1_WAYS_SHIFT   3
#define	CCSIDR_EL1_WAYS_MASK   BIT_MASK(10)
#define	CCSIDR_EL1_SETS_SHIFT   13
#define	CCSIDR_EL1_SETS_MASK   BIT_MASK(15)
#define	dc_ops(op, val)

Functions
static ALWAYS_INLINE size_t	arch_dcache_line_size_get (void)
static ALWAYS_INLINE int	arm64_dcache_range (void *addr, size_t size, int op)
static ALWAYS_INLINE int	arch_dcache_flush_all (void)
static ALWAYS_INLINE int	arch_dcache_invd_all (void)
static ALWAYS_INLINE int	arch_dcache_flush_and_invd_all (void)
static ALWAYS_INLINE int	arch_dcache_flush_range (void *addr, size_t size)
static ALWAYS_INLINE int	arch_dcache_invd_range (void *addr, size_t size)
static ALWAYS_INLINE int	arch_dcache_flush_and_invd_range (void *addr, size_t size)
static ALWAYS_INLINE void	arch_dcache_enable (void)
static ALWAYS_INLINE void	arch_dcache_disable (void)
static ALWAYS_INLINE void	arch_cache_init (void)

Variables
static size_t	dcache_line_size

Macro Definition Documentation

CCSIDR_EL1_LN_SZ_MASK

#define CCSIDR_EL1_LN_SZ_MASK   BIT_MASK(3)

CCSIDR_EL1_LN_SZ_SHIFT

#define CCSIDR_EL1_LN_SZ_SHIFT   0

CCSIDR_EL1_SETS_MASK

#define CCSIDR_EL1_SETS_MASK   BIT_MASK(15)

CCSIDR_EL1_SETS_SHIFT

#define CCSIDR_EL1_SETS_SHIFT   13

CCSIDR_EL1_WAYS_MASK

#define CCSIDR_EL1_WAYS_MASK   BIT_MASK(10)

CCSIDR_EL1_WAYS_SHIFT

#define CCSIDR_EL1_WAYS_SHIFT   3

CLIDR_EL1_CTYPE_MASK

#define CLIDR_EL1_CTYPE_MASK   BIT_MASK(3)

CLIDR_EL1_CTYPE_SHIFT

#define CLIDR_EL1_CTYPE_SHIFT

(

level

)

Value:

((level) * 3)

CLIDR_EL1_LOC_MASK

#define CLIDR_EL1_LOC_MASK   BIT_MASK(3)

CLIDR_EL1_LOC_SHIFT

#define CLIDR_EL1_LOC_SHIFT   24

CTR_EL0_CWG_MASK

#define CTR_EL0_CWG_MASK   BIT_MASK(4)

CTR_EL0_CWG_SHIFT

#define CTR_EL0_CWG_SHIFT   24

CTR_EL0_DMINLINE_MASK

#define CTR_EL0_DMINLINE_MASK   BIT_MASK(4)

CTR_EL0_DMINLINE_SHIFT

#define CTR_EL0_DMINLINE_SHIFT   16

dc_ops

#define dc_ops	(		op,
			val )

Value:

({                                                                      \
        __asm__ volatile ("dc " op ", %0" :: "r" (val) : "memory");     \
})

K_CACHE_INVD

#define K_CACHE_INVD   BIT(1)

K_CACHE_WB

#define K_CACHE_WB   BIT(0)

K_CACHE_WB_INVD

#define K_CACHE_WB_INVD   (K_CACHE_WB | K_CACHE_INVD)

Function Documentation

arch_cache_init()

ALWAYS_INLINE void arch_cache_init ( void )

static

arch_dcache_disable()

ALWAYS_INLINE void arch_dcache_disable ( void )

static

arch_dcache_enable()

ALWAYS_INLINE void arch_dcache_enable ( void )

static

arch_dcache_flush_all()

ALWAYS_INLINE int arch_dcache_flush_all ( void )

static

arch_dcache_flush_and_invd_all()

ALWAYS_INLINE int arch_dcache_flush_and_invd_all ( void )

static

arch_dcache_flush_and_invd_range()

ALWAYS_INLINE int arch_dcache_flush_and_invd_range ( void * addr, size_t size )

static

arch_dcache_flush_range()

ALWAYS_INLINE int arch_dcache_flush_range ( void * addr, size_t size )

static

arch_dcache_invd_all()

ALWAYS_INLINE int arch_dcache_invd_all ( void )

static

arch_dcache_invd_range()

ALWAYS_INLINE int arch_dcache_invd_range ( void * addr, size_t size )

static

arch_dcache_line_size_get()

ALWAYS_INLINE size_t arch_dcache_line_size_get ( void )

static

arm64_dcache_range()

ALWAYS_INLINE int arm64_dcache_range ( void * addr, size_t size, int op )

static

Variable Documentation

dcache_line_size

size_t dcache_line_size

static