Zephyr Project API 4.4.99
A Scalable Open Source RTOS
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Arm GIC interrupt controller devicetree macros. More...

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Macros

#define IRQ_TYPE_LEVEL   BIT(1)
 Level-triggered interrupt.
#define IRQ_TYPE_EDGE   BIT(2)
 Edge-triggered interrupt.
#define GIC_SPI   0x0
 Shared Peripheral Interrupt group.
#define GIC_PPI   0x1
 Private Peripheral Interrupt group.
#define IRQ_DEFAULT_PRIORITY   0xa0
 Default interrupt priority.
CPU interrupt numbers

Private peripheral interrupt (PPI) numbers for the Arm CPU interface.

#define GIC_INT_VIRT_MAINT   25
 Virtual maintenance interrupt.
#define GIC_INT_HYP_TIMER   26
 Hypervisor timer interrupt.
#define GIC_INT_VIRT_TIMER   27
 Virtual timer interrupt.
#define GIC_INT_LEGACY_FIQ   28
 Legacy nFIQ signal.
#define GIC_INT_PHYS_TIMER   29
 Secure physical timer interrupt.
#define GIC_INT_NS_PHYS_TIMER   30
 Non-secure physical timer interrupt (alias).
#define GIC_INT_LEGACY_IRQ   31
 Legacy nIRQ signal.

Detailed Description

Arm GIC interrupt controller devicetree macros.