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◆ A_BIT
◆ CNTV_CTL_ENABLE_BIT
#define CNTV_CTL_ENABLE_BIT BIT(0) |
◆ CNTV_CTL_IMASK_BIT
#define CNTV_CTL_IMASK_BIT BIT(1) |
◆ CPACR_CP10
#define CPACR_CP10 |
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r | ) |
(r << 20) |
◆ CPACR_CP11
#define CPACR_CP11 |
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r | ) |
(r << 22) |
◆ CPACR_FA
◆ CPACR_NA
◆ DFSR_AXI_SLAVE_MASK
#define DFSR_AXI_SLAVE_MASK (1 << 12) |
◆ DFSR_DOMAIN_MASK
#define DFSR_DOMAIN_MASK (0xf) |
◆ DFSR_DOMAIN_SHIFT
#define DFSR_DOMAIN_SHIFT (4) |
◆ DFSR_FAULT_4_MASK
#define DFSR_FAULT_4_MASK (1 << 10) |
◆ DFSR_WRITE_MASK
#define DFSR_WRITE_MASK (1 << 11) |
◆ E_BIT
◆ F_BIT
◆ FPEXC_EN
#define FPEXC_EN (1 << 30) |
◆ GET_MPIDR
◆ GICV3_SGIR_VALUE
#define GICV3_SGIR_VALUE |
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_aff3, |
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_aff2, |
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_aff1, |
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_intid, |
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_irm, |
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_tgt |
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Value:
#define SGIR_IRM_SHIFT
Definition cpu.h:115
#define SGIR_IRM_MASK
Definition cpu.h:116
#define SGIR_AFF1_SHIFT
Definition cpu.h:109
#define SGIR_INTID_MASK
Definition cpu.h:114
#define SGIR_INTID_SHIFT
Definition cpu.h:113
#define SGIR_AFF_MASK
Definition cpu.h:112
#define SGIR_AFF3_SHIFT
Definition cpu.h:111
#define SGIR_TGT_MASK
Definition cpu.h:108
#define SGIR_AFF2_SHIFT
Definition cpu.h:110
__UINT64_TYPE__ uint64_t
Definition stdint.h:91
◆ HACTLR_BUSTIMEOUTR_BIT
#define HACTLR_BUSTIMEOUTR_BIT BIT(10) |
◆ HACTLR_CDBGDCI
#define HACTLR_CDBGDCI BIT(1) |
◆ HACTLR_CPUACTLR
#define HACTLR_CPUACTLR BIT(0) |
◆ HACTLR_ERR_BIT
#define HACTLR_ERR_BIT BIT(13) |
◆ HACTLR_FLASHIFREGIONR
#define HACTLR_FLASHIFREGIONR BIT(7) |
◆ HACTLR_INIT
Value:
#define HACTLR_PERIPHPREGIONR
Definition cpu.h:74
#define HACTLR_CPUACTLR
Definition cpu.h:71
#define HACTLR_INTMONR_BIT
Definition cpu.h:77
#define HACTLR_FLASHIFREGIONR
Definition cpu.h:73
#define HACTLR_BUSTIMEOUTR_BIT
Definition cpu.h:76
#define HACTLR_QOSR_BIT
Definition cpu.h:75
#define HACTLR_ERR_BIT
Definition cpu.h:78
#define HACTLR_CDBGDCI
Definition cpu.h:72
◆ HACTLR_INTMONR_BIT
#define HACTLR_INTMONR_BIT BIT(12) |
◆ HACTLR_PERIPHPREGIONR
#define HACTLR_PERIPHPREGIONR BIT(8) |
◆ HACTLR_QOSR_BIT
#define HACTLR_QOSR_BIT BIT(9) |
◆ HIVECS
◆ HSCTLR_RES1
Value:
BIT(22) |
BIT(18) |
BIT(16) | \
#define BIT(n)
Unsigned integer with bit position n set (signed in assembly language).
Definition util_macro.h:44
◆ I_BIT
◆ ICC_SRE_EL3_EN_BIT
#define ICC_SRE_EL3_EN_BIT BIT(3) |
◆ ICC_SRE_ELx_DFB_BIT
#define ICC_SRE_ELx_DFB_BIT BIT(1) |
◆ ICC_SRE_ELx_DIB_BIT
#define ICC_SRE_ELx_DIB_BIT BIT(2) |
◆ ICC_SRE_ELx_SRE_BIT
#define ICC_SRE_ELx_SRE_BIT BIT(0) |
◆ IMP_CSCTLR
#define IMP_CSCTLR |
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iway, |
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dway |
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Value:
#define IMP_CSCTLR_DFLW_SHIFT
Definition cpu.h:60
#define IMP_CSCTLR_IFLW_SHIFT
Definition cpu.h:61
◆ IMP_CSCTLR_DFLW_SHIFT
#define IMP_CSCTLR_DFLW_SHIFT (0) |
◆ IMP_CSCTLR_IFLW_SHIFT
#define IMP_CSCTLR_IFLW_SHIFT (8) |
◆ MODE_ABT
◆ MODE_FIQ
◆ MODE_HYP
◆ MODE_IRQ
◆ MODE_MASK
◆ MODE_SVC
◆ MODE_SYS
◆ MODE_UND
◆ MODE_USR
◆ MPIDR_AFF0_SHIFT
#define MPIDR_AFF0_SHIFT (0) |
◆ MPIDR_AFF1_SHIFT
#define MPIDR_AFF1_SHIFT (8) |
◆ MPIDR_AFF2_SHIFT
#define MPIDR_AFF2_SHIFT (16) |
◆ MPIDR_AFFLVL
#define MPIDR_AFFLVL |
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mpidr, |
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aff_level |
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| (((mpidr) >> MPIDR_AFF##aff_level##_SHIFT) & MPIDR_AFFLVL_MASK) |
◆ MPIDR_AFFLVL_MASK
#define MPIDR_AFFLVL_MASK (0xffffff) |
◆ MPIDR_TO_CORE
◆ SCTLR_A_BIT
#define SCTLR_A_BIT BIT(1) |
◆ SCTLR_C_BIT
#define SCTLR_C_BIT BIT(2) |
◆ SCTLR_I_BIT
#define SCTLR_I_BIT BIT(12) |
◆ SCTLR_M_BIT
#define SCTLR_M_BIT BIT(0) |
◆ SCTLR_MPU_ENABLE
#define SCTLR_MPU_ENABLE (1 << 0) |
◆ SGIR_AFF1_SHIFT
#define SGIR_AFF1_SHIFT (16) |
◆ SGIR_AFF2_SHIFT
#define SGIR_AFF2_SHIFT (32) |
◆ SGIR_AFF3_SHIFT
#define SGIR_AFF3_SHIFT (48) |
◆ SGIR_AFF_MASK
#define SGIR_AFF_MASK (0xff) |
◆ SGIR_INTID_MASK
#define SGIR_INTID_MASK (0xf) |
◆ SGIR_INTID_SHIFT
#define SGIR_INTID_SHIFT (24) |
◆ SGIR_IRM_MASK
#define SGIR_IRM_MASK (0x1) |
◆ SGIR_IRM_SHIFT
#define SGIR_IRM_SHIFT (40) |
◆ SGIR_IRM_TO_AFF
#define SGIR_IRM_TO_AFF (0) |
◆ SGIR_TGT_MASK
#define SGIR_TGT_MASK (0xffff) |
◆ T_BIT
◆ VBAR_MASK
#define VBAR_MASK (0xFFFFFFE0U) |