Zephyr Project API 4.4.99
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arm_mpu_v8.h
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1/*
2 * Copyright (c) 2018 Linaro Limited.
3 * Copyright (c) 2018 Nordic Semiconductor ASA.
4 * Copyright 2025 Arm Limited and/or its affiliates <open-source-office@arm.com>
5 *
6 * SPDX-License-Identifier: Apache-2.0
7 */
8
9#ifndef ZEPHYR_INCLUDE_ARCH_ARM_MPU_ARM_MPU_V8_H_
10#define ZEPHYR_INCLUDE_ARCH_ARM_MPU_ARM_MPU_V8_H_
11
12#ifndef _ASMLANGUAGE
13
14/* Convenience macros to represent the ARMv8-M-specific
15 * configuration for memory access permission and
16 * cache-ability attribution.
17 */
18#if defined(CONFIG_AARCH32_ARMV8_R)
19#define MPU_IR_REGION_Msk (0xFFU)
20#define MPU_IR_REGION_Pos 8U
21/* MPU RBAR Register attribute msk Definitions */
22#define MPU_RBAR_BASE_Pos 6U
23#define MPU_RBAR_BASE_Msk (0x3FFFFFFFFFFFFFFUL << MPU_RBAR_BASE_Pos)
24#define MPU_RBAR_SH_Pos 3U
25#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos)
26#define MPU_RBAR_AP_Pos 1U
27#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos)
28/* RBAR XN */
29#define MPU_RBAR_XN_Pos 0U
30#define MPU_RBAR_XN_Msk (0x1UL << MPU_RBAR_XN_Pos)
31
32/* MPU PLBAR Register Definitions */
33#define MPU_RLAR_LIMIT_Pos 6U
34#define MPU_RLAR_LIMIT_Msk (0x3FFFFFFFFFFFFFFUL << MPU_RLAR_LIMIT_Pos)
35#define MPU_RLAR_AttrIndx_Pos 1U
36#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos)
37#define MPU_RLAR_EN_Msk (0x1UL)
38#else
39#include <cmsis_core.h>
40#endif
41
42/* Privileged No Access, Unprivileged No Access */
43/*#define NO_ACCESS 0x0 */
44/*#define NO_ACCESS_Msk ((NO_ACCESS << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) */
45/* Privileged No Access, Unprivileged No Access */
46/*#define P_NA_U_NA 0x0 */
47/*#define P_NA_U_NA_Msk ((P_NA_U_NA << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) */
48/* Privileged Read Write, Unprivileged No Access */
49#define P_RW_U_NA 0x0
50#define P_RW_U_NA_Msk ((P_RW_U_NA << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk)
51/* Privileged Read Write, Unprivileged Read Only */
52/*#define P_RW_U_RO 0x2 */
53/*#define P_RW_U_RO_Msk ((P_RW_U_RO << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk)*/
54/* Privileged Read Write, Unprivileged Read Write */
55#define P_RW_U_RW 0x1
56#define P_RW_U_RW_Msk ((P_RW_U_RW << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk)
57/* Privileged Read Write, Unprivileged Read Write */
58#define FULL_ACCESS 0x1
59#define FULL_ACCESS_Msk ((FULL_ACCESS << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk)
60/* Privileged Read Only, Unprivileged No Access */
61#define P_RO_U_NA 0x2
62#define P_RO_U_NA_Msk ((P_RO_U_NA << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk)
63/* Privileged Read Only, Unprivileged Read Only */
64#define P_RO_U_RO 0x3
65#define P_RO_U_RO_Msk ((P_RO_U_RO << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk)
66/* Privileged Read Only, Unprivileged Read Only */
67#define RO 0x3
68#define RO_Msk ((RO << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk)
69
70/* Attribute flag for not-allowing execution (eXecute Never) */
71#define NOT_EXEC MPU_RBAR_XN_Msk
72
73/* To prevent execution of MPU region in privileged mode */
74#define PRIV_EXEC_NEVER (1)
75
76/* Attribute flags for share-ability */
77#define NON_SHAREABLE 0x0
78#define NON_SHAREABLE_Msk ((NON_SHAREABLE << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk)
79#define OUTER_SHAREABLE 0x2
80#define OUTER_SHAREABLE_Msk ((OUTER_SHAREABLE << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk)
81#define INNER_SHAREABLE 0x3
82#define INNER_SHAREABLE_Msk ((INNER_SHAREABLE << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk)
83
84/* Helper define to calculate the region limit address. */
85#define REGION_LIMIT_ADDR(base, size) (((base & MPU_RBAR_BASE_Msk) + size - 1) & MPU_RLAR_LIMIT_Msk)
86
87/* Attribute flags for cache-ability */
88
89/* Memory Attributes for Device Memory
90 * 1.Gathering (G/nG)
91 * Determines whether multiple accesses can be merged into a single
92 * bus transaction.
93 * nG: Number/size of accesses on the bus = number/size of accesses
94 * in code.
95 *
96 * 2.Reordering (R/nR)
97 * Determines whether accesses to the same device can be reordered.
98 * nR: Accesses to the same IMPLEMENTATION DEFINED block size will
99 * appear on the bus in program order.
100 *
101 * 3 Early Write Acknowledgment (E/nE)
102 * Indicates to the memory system whether a buffer can send
103 * acknowledgements.
104 * nE: The response should come from the end slave, not buffering in
105 * the interconnect.
106 */
107#define DEVICE_nGnRnE 0x0U
108#define DEVICE_nGnRE 0x4U
109#define DEVICE_nGRE 0x8U
110#define DEVICE_GRE 0xCU
111
112/* Read/Write Allocation Configurations for Cacheable Memory */
113#define R_NON_W_NON 0x0 /* Do not allocate Read/Write */
114#define R_NON_W_ALLOC 0x1 /* Do not allocate Read, Allocate Write */
115#define R_ALLOC_W_NON 0x2 /* Allocate Read, Do not allocate Write */
116#define R_ALLOC_W_ALLOC 0x3 /* Allocate Read/Write */
117
118/* Memory Attributes for Normal Memory */
119#define NORMAL_O_WT_NT 0x80 /* Normal, Outer Write-through non-transient */
120#define NORMAL_O_WB_NT 0xC0 /* Normal, Outer Write-back non-transient */
121#define NORMAL_O_NON_C 0x40 /* Normal, Outer Non-Cacheable */
122
123#define NORMAL_I_WT_NT 0x08 /* Normal, Inner Write-through non-transient */
124#define NORMAL_I_WB_NT 0x0C /* Normal, Inner Write-back non-transient */
125#define NORMAL_I_NON_C 0x04 /* Normal, Inner Non-Cacheable */
126
127#define NORMAL_OUTER_INNER_WRITE_THROUGH_READ_ALLOCATE_NON_TRANS \
128 ((NORMAL_O_WT_NT | (R_ALLOC_W_NON << 4)) | (NORMAL_I_WT_NT | R_ALLOC_W_NON))
129
130#define NORMAL_OUTER_INNER_WRITE_BACK_WRITE_READ_ALLOCATE_NON_TRANS \
131 ((NORMAL_O_WB_NT | (R_ALLOC_W_ALLOC << 4)) | (NORMAL_I_WB_NT | R_ALLOC_W_ALLOC))
132
133#define NORMAL_OUTER_INNER_NON_CACHEABLE \
134 ((NORMAL_O_NON_C | (R_NON_W_NON << 4)) | (NORMAL_I_NON_C | R_NON_W_NON))
135
136/* Common cache-ability configuration for Flash, SRAM regions */
137#define MPU_CACHE_ATTRIBUTES_FLASH NORMAL_OUTER_INNER_WRITE_THROUGH_READ_ALLOCATE_NON_TRANS
138/* clang-format off */
139#define MPU_CACHE_ATTRIBUTES_SRAM \
140 NORMAL_OUTER_INNER_WRITE_BACK_WRITE_READ_ALLOCATE_NON_TRANS
141/* clang-format on */
142#define MPU_CACHE_ATTRIBUTES_SRAM_NOCACHE NORMAL_OUTER_INNER_NON_CACHEABLE
143
144/* Global MAIR configurations */
145#define MPU_MAIR_ATTR_FLASH MPU_CACHE_ATTRIBUTES_FLASH
146#define MPU_MAIR_INDEX_FLASH 0
147#define MPU_MAIR_ATTR_SRAM MPU_CACHE_ATTRIBUTES_SRAM
148#define MPU_MAIR_INDEX_SRAM 1
149#define MPU_MAIR_ATTR_SRAM_NOCACHE MPU_CACHE_ATTRIBUTES_SRAM_NOCACHE
150#define MPU_MAIR_INDEX_SRAM_NOCACHE 2
151#define MPU_MAIR_ATTR_DEVICE DEVICE_nGnRnE
152#define MPU_MAIR_INDEX_DEVICE 3
153/* Flash region(s): Attribute-0
154 * SRAM region(s): Attribute-1
155 * SRAM no cache-able regions(s): Attribute-2
156 * DEVICE no cache-able regions(s): Attribute-3
157 */
158#define MPU_MAIR_ATTRS \
159 ((MPU_MAIR_ATTR_FLASH << (MPU_MAIR_INDEX_FLASH * 8)) | \
160 (MPU_MAIR_ATTR_SRAM << (MPU_MAIR_INDEX_SRAM * 8)) | \
161 (MPU_MAIR_ATTR_SRAM_NOCACHE << (MPU_MAIR_INDEX_SRAM_NOCACHE * 8)) | \
162 (MPU_MAIR_ATTR_DEVICE << (MPU_MAIR_INDEX_DEVICE * 8)))
163
164/* Some helper defines for common regions.
165 *
166 * Note that the ARMv8-M/R MPU architecture requires that the
167 * enabled MPU regions are non-overlapping. Therefore, it is
168 * recommended to use these helper defines only for configuring
169 * fixed MPU regions at build-time (i.e. regions that are not
170 * expected to be re-programmed or re-adjusted at run-time so
171 * that they do not overlap with other MPU regions).
172 */
173#if defined(CONFIG_AARCH32_ARMV8_R)
174
175#define ARM_MPU_REGION_INIT(p_name, p_base, p_size, p_attr) \
176 { \
177 .name = p_name, \
178 .base = p_base, \
179 .attr = p_attr(p_base + p_size), \
180 }
181
182#define REGION_RAM_ATTR(limit) \
183 { \
184 .rbar = NOT_EXEC | P_RW_U_NA_Msk | NON_SHAREABLE_Msk, /* AP, XN, SH */ \
185 .mair_idx = MPU_MAIR_INDEX_SRAM, /* Cache-ability */ \
186 .r_limit = limit - 1, /* Region Limit */ \
187 }
188
189#define REGION_RAM_TEXT_ATTR(limit) \
190 { \
191 .rbar = P_RO_U_RO_Msk | NON_SHAREABLE_Msk, /* AP, XN, SH */ \
192 .mair_idx = MPU_MAIR_INDEX_SRAM, /* Cache-ability */ \
193 .r_limit = limit - 1, /* Region Limit */ \
194 }
195
196#define REGION_RAM_RO_ATTR(limit) \
197 { \
198 .rbar = NOT_EXEC | P_RO_U_RO_Msk | NON_SHAREABLE_Msk, /* AP, XN, SH */ \
199 .mair_idx = MPU_MAIR_INDEX_SRAM, /* Cache-ability */ \
200 .r_limit = limit - 1, /* Region Limit */ \
201 }
202#define REGION_RAM_NOCACHE_ATTR(limit) \
203 { \
204 .rbar = NOT_EXEC | P_RW_U_NA_Msk | NON_SHAREABLE_Msk, /* AP, XN, SH */ \
205 .mair_idx = MPU_MAIR_INDEX_SRAM_NOCACHE, /* Cache-ability */ \
206 .r_limit = limit - 1, /* Region Limit */ \
207 }
208#if defined(CONFIG_MPU_ALLOW_FLASH_WRITE)
209/* Note that the access permissions allow for un-privileged writes, contrary
210 * to ARMv7-M where un-privileged code has Read-Only permissions.
211 */
212#define REGION_FLASH_ATTR(limit) \
213 { \
214 .rbar = P_RW_U_RW_Msk | NON_SHAREABLE_Msk, /* AP, XN, SH */ \
215 .mair_idx = MPU_MAIR_INDEX_FLASH, /* Cache-ability */ \
216 .r_limit = limit - 1, /* Region Limit */ \
217 }
218#else /* CONFIG_MPU_ALLOW_FLASH_WRITE */
219#define REGION_FLASH_ATTR(limit) \
220 { \
221 .rbar = RO_Msk | NON_SHAREABLE_Msk, /* AP, XN, SH */ \
222 .mair_idx = MPU_MAIR_INDEX_FLASH, /* Cache-ability */ \
223 .r_limit = limit - 1, /* Region Limit */ \
224 }
225#endif /* CONFIG_MPU_ALLOW_FLASH_WRITE */
226
227#define REGION_DEVICE_ATTR(limit) \
228 { \
229 .rbar = NOT_EXEC | P_RW_U_NA_Msk | NON_SHAREABLE_Msk, /* AP, XN, SH */ \
230 .mair_idx = MPU_MAIR_INDEX_DEVICE, /* Cache-ability */ \
231 .r_limit = limit - 1, /* Region Limit */ \
232 }
233#else
234
235#define ARM_MPU_REGION_INIT(p_name, p_base, p_size, p_attr) \
236 { \
237 .name = p_name, \
238 .base = p_base, \
239 .attr = p_attr(p_base, p_size), \
240 }
241
242/* On Cortex-M, we can only set the XN bit when CONFIG_XIP=y. When
243 * CONFIG_XIP=n, the entire image will be linked to SRAM, so we need to keep
244 * the SRAM region XN bit clear or the application code will not be executable.
245 */
246/* clang-format off */
247#define REGION_RAM_ATTR(base, size) \
248 { \
249 .rbar = IF_ENABLED(CONFIG_XIP, (NOT_EXEC |)) P_RW_U_NA_Msk | \
250 NON_SHAREABLE_Msk, /* AP, XN, SH */ \
251 .mair_idx = MPU_MAIR_INDEX_SRAM, /* Cache-ability */ \
252 .r_limit = REGION_LIMIT_ADDR(base, size), /* Region Limit */ \
253 IF_ENABLED(CONFIG_ARM_MPU_PXN, (.pxn = !PRIV_EXEC_NEVER,)) \
254 }
255
256#define REGION_RAM_WT_ATTR(base, size) \
257 { \
258 .rbar = IF_ENABLED(CONFIG_XIP, (NOT_EXEC |)) P_RW_U_NA_Msk | \
259 NON_SHAREABLE_Msk, /* AP, XN, SH */ \
260 .mair_idx = MPU_MAIR_INDEX_FLASH, /* Cache-ability */ \
261 .r_limit = REGION_LIMIT_ADDR(base, size), /* Region Limit */ \
262 IF_ENABLED(CONFIG_ARM_MPU_PXN, (.pxn = !PRIV_EXEC_NEVER,)) \
263 }
264
266#define REGION_IO_ATTR(base, size) \
267 { \
268 .rbar = NOT_EXEC | P_RW_U_NA_Msk, /* AP, XN (SH ignored) */ \
269 .mair_idx = MPU_MAIR_INDEX_DEVICE, /* Cache-ability */ \
270 .r_limit = REGION_LIMIT_ADDR(base, size), /* Region Limit */ \
271 IF_ENABLED(CONFIG_ARM_MPU_PXN, (.pxn = PRIV_EXEC_NEVER,)) \
272 }
273
277#define REGION_RAM_ATTR_WITH_EXEC(base, size) \
278 { \
279 .rbar = P_RW_U_NA_Msk | NON_SHAREABLE_Msk, /* AP, SH */ \
280 .mair_idx = MPU_MAIR_INDEX_SRAM, /* Cache-ability */ \
281 .r_limit = REGION_LIMIT_ADDR(base, size), /* Region Limit */ \
282 IF_ENABLED(CONFIG_ARM_MPU_PXN, (.pxn = !PRIV_EXEC_NEVER,)) \
283 }
285
286#if defined(CONFIG_ARM_MPU_PXN)
287/* Use this attr to define an MPU region in RAM that has code intended to be executed in
288 * un-privileged mode but not in privileged mode.
289 */
290#define REGION_RAM_ATTR_PXN(base, size) \
291 { \
292 .rbar = P_RO_U_RO_Msk | NON_SHAREABLE_Msk,/* AP, XN, SH */ \
293 .mair_idx = MPU_MAIR_INDEX_SRAM, /* Cache-ability */ \
294 .r_limit = REGION_LIMIT_ADDR(base, size), /* Region Limit */ \
295 .pxn = PRIV_EXEC_NEVER, \
296 }
297
298#define REGION_RAM_WT_ATTR_PXN(base, size) \
299 { \
300 .rbar = P_RO_U_RO_Msk | NON_SHAREABLE_Msk,/* AP, XN, SH */ \
301 .mair_idx = MPU_MAIR_INDEX_FLASH, /* Cache-ability */ \
302 .r_limit = REGION_LIMIT_ADDR(base, size), /* Region Limit */ \
303 .pxn = PRIV_EXEC_NEVER, \
304 }
305#endif
306
307#define REGION_RAM_NOCACHE_ATTR(base, size) \
308 { \
309 .rbar = NOT_EXEC | P_RW_U_NA_Msk | NON_SHAREABLE_Msk, /* AP, XN, SH */ \
310 .mair_idx = MPU_MAIR_INDEX_SRAM_NOCACHE, /* Cache-ability */ \
311 .r_limit = REGION_LIMIT_ADDR(base, size), /* Region Limit */ \
312 IF_ENABLED(CONFIG_ARM_MPU_PXN, (.pxn = PRIV_EXEC_NEVER,)) \
313 }
314
315#if defined(CONFIG_MPU_ALLOW_FLASH_WRITE)
316/* Note that the access permissions allow for un-privileged writes, contrary
317 * to ARMv7-M where un-privileged code has Read-Only permissions.
318 */
319#define REGION_FLASH_ATTR(base, size) \
320 { \
321 .rbar = P_RW_U_RW_Msk | NON_SHAREABLE_Msk, /* AP, XN, SH */ \
322 .mair_idx = MPU_MAIR_INDEX_FLASH, /* Cache-ability */ \
323 .r_limit = REGION_LIMIT_ADDR(base, size), /* Region Limit */ \
324 IF_ENABLED(CONFIG_ARM_MPU_PXN, (.pxn = !PRIV_EXEC_NEVER,)) \
325 }
326
327#else /* CONFIG_MPU_ALLOW_FLASH_WRITE */
328#define REGION_FLASH_ATTR(base, size) \
329 { \
330 .rbar = RO_Msk | NON_SHAREABLE_Msk, /* AP, XN, SH */ \
331 .mair_idx = MPU_MAIR_INDEX_FLASH, /* Cache-ability */ \
332 .r_limit = REGION_LIMIT_ADDR(base, size), /* Region Limit */ \
333 IF_ENABLED(CONFIG_ARM_MPU_PXN, (.pxn = !PRIV_EXEC_NEVER,)) \
334 }
335
336#endif /* CONFIG_MPU_ALLOW_FLASH_WRITE */
337
338#define REGION_DEVICE_ATTR(base, size) \
339 { \
340 .rbar = NOT_EXEC | P_RW_U_NA_Msk | NON_SHAREABLE_Msk, /* AP, XN, SH */ \
341 .mair_idx = MPU_MAIR_INDEX_DEVICE, /* Cache-ability */ \
342 .r_limit = REGION_LIMIT_ADDR(base, size), /* Region Limit */ \
343 IF_ENABLED(CONFIG_ARM_MPU_PXN, (.pxn = PRIV_EXEC_NEVER,)) \
344 }
345
346/* clang-format on */
347#endif
348
349struct arm_mpu_region_attr {
350 /* Attributes belonging to RBAR */
351 uint8_t rbar: 5;
352 /* MAIR index for attribute indirection */
353 uint8_t mair_idx: 3;
354 /* Region Limit Address value to be written to the RLAR register. */
355 uint32_t r_limit;
356#ifdef CONFIG_ARM_MPU_PXN
357 /* To prevent execution of MPU region in privileged mode (Privileged Execute Never) */
358 uint8_t pxn;
359#endif
360};
361
362typedef struct arm_mpu_region_attr arm_mpu_region_attr_t;
363
364/* Typedef for the k_mem_partition attribute */
365typedef struct {
366 uint16_t rbar;
367 uint16_t mair_idx;
368#ifdef CONFIG_ARM_MPU_PXN
369 /* To prevent execution of MPU region in privileged mode (Privileged Execute Never) */
370 uint8_t pxn;
371#endif
372} k_mem_partition_attr_t;
373
374/* Kernel macros for memory attribution
375 * (access permissions and cache-ability).
376 *
377 * The macros are to be stored in k_mem_partition_attr_t
378 * objects. The format of a k_mem_partition_attr_t object
379 * is as follows: field <rbar> contains a direct mapping
380 * of the <XN> and <AP> bit-fields of the RBAR register;
381 * field <mair_idx> contains a direct mapping of AttrIdx
382 * bit-field, stored in RLAR register.
383 */
384
385/* Read-Write access permission attributes */
386#define K_MEM_PARTITION_P_RW_U_RW \
387 ((k_mem_partition_attr_t){(P_RW_U_RW_Msk | NOT_EXEC), MPU_MAIR_INDEX_SRAM})
388#define K_MEM_PARTITION_P_RW_U_NA \
389 ((k_mem_partition_attr_t){(P_RW_U_NA_Msk | NOT_EXEC), MPU_MAIR_INDEX_SRAM})
390#define K_MEM_PARTITION_P_RO_U_RO \
391 ((k_mem_partition_attr_t){(P_RO_U_RO_Msk | NOT_EXEC), MPU_MAIR_INDEX_SRAM})
392#define K_MEM_PARTITION_P_RO_U_NA \
393 ((k_mem_partition_attr_t){(P_RO_U_NA_Msk | NOT_EXEC), MPU_MAIR_INDEX_SRAM})
394
395/* Execution-allowed attributes */
396#define K_MEM_PARTITION_P_RWX_U_RWX ((k_mem_partition_attr_t){(P_RW_U_RW_Msk), MPU_MAIR_INDEX_SRAM})
397#define K_MEM_PARTITION_P_RX_U_RX ((k_mem_partition_attr_t){(P_RO_U_RO_Msk), MPU_MAIR_INDEX_SRAM})
398
399#ifdef CONFIG_ARM_MPU_PXN
400#define K_MEM_PARTITION_P_R_U_RX \
401 ((k_mem_partition_attr_t){(P_RO_U_RO_Msk), MPU_MAIR_INDEX_SRAM, PRIV_EXEC_NEVER})
402#endif
403
404/*
405 * @brief Evaluate Write-ability
406 *
407 * Evaluate whether the access permissions include write-ability.
408 *
409 * @param attr The k_mem_partition_attr_t object holding the
410 * MPU attributes to be checked against write-ability.
411 */
412#define K_MEM_PARTITION_IS_WRITABLE(attr) \
413 ({ \
414 int __is_writable__; \
415 switch (attr.rbar & MPU_RBAR_AP_Msk) { \
416 case P_RW_U_RW_Msk: \
417 case P_RW_U_NA_Msk: \
418 __is_writable__ = 1; \
419 break; \
420 default: \
421 __is_writable__ = 0; \
422 } \
423 __is_writable__; \
424 })
425
426/*
427 * @brief Evaluate Execution allowance
428 *
429 * Evaluate whether the access permissions include execution.
430 *
431 * @param attr The k_mem_partition_attr_t object holding the
432 * MPU attributes to be checked against execution
433 * allowance.
434 */
435#define K_MEM_PARTITION_IS_EXECUTABLE(attr) (!((attr.rbar) & (NOT_EXEC)))
436
437/* Attributes for no-cache enabling (share-ability is selected by default) */
438
439/* Read-Write access permission attributes */
440#define K_MEM_PARTITION_P_RW_U_RW_NOCACHE \
441 ((k_mem_partition_attr_t){(P_RW_U_RW_Msk | NOT_EXEC | OUTER_SHAREABLE_Msk), \
442 MPU_MAIR_INDEX_SRAM_NOCACHE})
443#define K_MEM_PARTITION_P_RW_U_NA_NOCACHE \
444 ((k_mem_partition_attr_t){(P_RW_U_NA_Msk | NOT_EXEC | OUTER_SHAREABLE_Msk), \
445 MPU_MAIR_INDEX_SRAM_NOCACHE})
446#define K_MEM_PARTITION_P_RO_U_RO_NOCACHE \
447 ((k_mem_partition_attr_t){(P_RO_U_RO_Msk | NOT_EXEC | OUTER_SHAREABLE_Msk), \
448 MPU_MAIR_INDEX_SRAM_NOCACHE})
449#define K_MEM_PARTITION_P_RO_U_NA_NOCACHE \
450 ((k_mem_partition_attr_t){(P_RO_U_NA_Msk | NOT_EXEC | OUTER_SHAREABLE_Msk), \
451 MPU_MAIR_INDEX_SRAM_NOCACHE})
452
453/* Execution-allowed attributes */
454#define K_MEM_PARTITION_P_RWX_U_RWX_NOCACHE \
455 ((k_mem_partition_attr_t){(P_RW_U_RW_Msk | OUTER_SHAREABLE_Msk), \
456 MPU_MAIR_INDEX_SRAM_NOCACHE})
457#define K_MEM_PARTITION_P_RX_U_RX_NOCACHE \
458 ((k_mem_partition_attr_t){(P_RO_U_RO_Msk | OUTER_SHAREABLE_Msk), \
459 MPU_MAIR_INDEX_SRAM_NOCACHE})
460
461#endif /* _ASMLANGUAGE */
462
463
464/* Some compilers do not handle casts on pointers in constant expressions */
465#if defined(__IAR_SYSTEMS_ICC__)
466#define _ARCH_MEM_PARTITION_ALIGN_CHECK(start, size) \
467 BUILD_ASSERT( \
468 (size > 0) && \
469 ((size) % CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE == 0), \
470 "The start and size of the partition must align with the minimum MPU " \
471 "region size.")
472#else
473#define _ARCH_MEM_PARTITION_ALIGN_CHECK(start, size) \
474 BUILD_ASSERT((size > 0) && \
475 ((uint32_t)start % CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE == 0U) && \
476 ((size) % CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE == 0), \
477 "The start and size of the partition must align with the minimum MPU " \
478 "region size.")
479#endif /* defined(__IAR_SYSTEMS_ICC__) */
480
481#endif /* ZEPHYR_INCLUDE_ARCH_ARM_MPU_ARM_MPU_V8_H_ */
arm_mpu_region_attr_t
struct arm_mpu_region_attr arm_mpu_region_attr_t
Definition arm_mpu_v7m.h:145
uint32_t
__UINT32_TYPE__ uint32_t
Definition stdint.h:90
uint8_t
__UINT8_TYPE__ uint8_t
Definition stdint.h:88
uint16_t
__UINT16_TYPE__ uint16_t
Definition stdint.h:89
arm_mpu_region_attr
Definition arm_mpu_v7m.h:140
arm_mpu_region_attr::rbar
uint8_t rbar
Definition arm_mpu_v8.h:351
arm_mpu_region_attr::r_limit
uint32_t r_limit
Definition arm_mpu_v8.h:355
arm_mpu_region_attr::mair_idx
uint8_t mair_idx
Definition arm_mpu_v8.h:353
k_mem_partition_attr_t
Definition arm_mpu_v7m.h:148
k_mem_partition_attr_t::rbar
uint16_t rbar
Definition arm_mpu_v8.h:366
k_mem_partition_attr_t::mair_idx
uint16_t mair_idx
Definition arm_mpu_v8.h:367