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#define | P_RW_U_NA 0x0 |
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#define | P_RW_U_NA_Msk ((P_RW_U_NA << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) |
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#define | P_RW_U_RW 0x1 |
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#define | P_RW_U_RW_Msk ((P_RW_U_RW << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) |
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#define | FULL_ACCESS 0x1 |
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#define | FULL_ACCESS_Msk ((FULL_ACCESS << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) |
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#define | P_RO_U_NA 0x2 |
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#define | P_RO_U_NA_Msk ((P_RO_U_NA << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) |
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#define | P_RO_U_RO 0x3 |
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#define | P_RO_U_RO_Msk ((P_RO_U_RO << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) |
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#define | RO 0x3 |
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#define | RO_Msk ((RO << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) |
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#define | NOT_EXEC MPU_RBAR_XN_Msk |
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#define | NON_SHAREABLE 0x0 |
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#define | NON_SHAREABLE_Msk ((NON_SHAREABLE << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) |
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#define | OUTER_SHAREABLE 0x2 |
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#define | OUTER_SHAREABLE_Msk ((OUTER_SHAREABLE << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) |
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#define | INNER_SHAREABLE 0x3 |
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#define | INNER_SHAREABLE_Msk ((INNER_SHAREABLE << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) |
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#define | REGION_LIMIT_ADDR(base, size) (((base & MPU_RBAR_BASE_Msk) + size - 1) & MPU_RLAR_LIMIT_Msk) |
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#define | DEVICE_nGnRnE 0x0U |
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#define | DEVICE_nGnRE 0x4U |
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#define | DEVICE_nGRE 0x8U |
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#define | DEVICE_GRE 0xCU |
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#define | R_NON_W_NON 0x0 /* Do not allocate Read/Write */ |
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#define | R_NON_W_ALLOC 0x1 /* Do not allocate Read, Allocate Write */ |
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#define | R_ALLOC_W_NON 0x2 /* Allocate Read, Do not allocate Write */ |
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#define | R_ALLOC_W_ALLOC 0x3 /* Allocate Read/Write */ |
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#define | NORMAL_O_WT_NT 0x80 /* Normal, Outer Write-through non-transient */ |
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#define | NORMAL_O_WB_NT 0xC0 /* Normal, Outer Write-back non-transient */ |
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#define | NORMAL_O_NON_C 0x40 /* Normal, Outer Non-Cacheable */ |
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#define | NORMAL_I_WT_NT 0x08 /* Normal, Inner Write-through non-transient */ |
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#define | NORMAL_I_WB_NT 0x0C /* Normal, Inner Write-back non-transient */ |
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#define | NORMAL_I_NON_C 0x04 /* Normal, Inner Non-Cacheable */ |
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#define | NORMAL_OUTER_INNER_WRITE_THROUGH_READ_ALLOCATE_NON_TRANS |
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#define | NORMAL_OUTER_INNER_WRITE_BACK_WRITE_READ_ALLOCATE_NON_TRANS |
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#define | NORMAL_OUTER_INNER_NON_CACHEABLE |
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#define | MPU_CACHE_ATTRIBUTES_FLASH NORMAL_OUTER_INNER_WRITE_THROUGH_READ_ALLOCATE_NON_TRANS |
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#define | MPU_CACHE_ATTRIBUTES_SRAM NORMAL_OUTER_INNER_WRITE_BACK_WRITE_READ_ALLOCATE_NON_TRANS |
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#define | MPU_CACHE_ATTRIBUTES_SRAM_NOCACHE NORMAL_OUTER_INNER_NON_CACHEABLE |
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#define | MPU_MAIR_ATTR_FLASH MPU_CACHE_ATTRIBUTES_FLASH |
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#define | MPU_MAIR_INDEX_FLASH 0 |
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#define | MPU_MAIR_ATTR_SRAM MPU_CACHE_ATTRIBUTES_SRAM |
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#define | MPU_MAIR_INDEX_SRAM 1 |
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#define | MPU_MAIR_ATTR_SRAM_NOCACHE MPU_CACHE_ATTRIBUTES_SRAM_NOCACHE |
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#define | MPU_MAIR_INDEX_SRAM_NOCACHE 2 |
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#define | MPU_MAIR_ATTR_DEVICE DEVICE_nGnRnE |
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#define | MPU_MAIR_INDEX_DEVICE 3 |
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#define | MPU_MAIR_ATTRS |
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#define | ARM_MPU_REGION_INIT(p_name, p_base, p_size, p_attr) |
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#define | REGION_RAM_ATTR(base, size) |
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#define | REGION_RAM_NOCACHE_ATTR(base, size) |
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#define | REGION_FLASH_ATTR(base, size) |
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#define | REGION_DEVICE_ATTR(base, size) |
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#define | K_MEM_PARTITION_P_RW_U_RW |
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#define | K_MEM_PARTITION_P_RW_U_NA |
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#define | K_MEM_PARTITION_P_RO_U_RO |
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#define | K_MEM_PARTITION_P_RO_U_NA |
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#define | K_MEM_PARTITION_P_RWX_U_RWX |
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#define | K_MEM_PARTITION_P_RX_U_RX |
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#define | K_MEM_PARTITION_IS_WRITABLE(attr) |
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#define | K_MEM_PARTITION_IS_EXECUTABLE(attr) (!((attr.rbar) & (NOT_EXEC))) |
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#define | K_MEM_PARTITION_P_RW_U_RW_NOCACHE |
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#define | K_MEM_PARTITION_P_RW_U_NA_NOCACHE |
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#define | K_MEM_PARTITION_P_RO_U_RO_NOCACHE |
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#define | K_MEM_PARTITION_P_RO_U_NA_NOCACHE |
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#define | K_MEM_PARTITION_P_RWX_U_RWX_NOCACHE |
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#define | K_MEM_PARTITION_P_RX_U_RX_NOCACHE |
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