bflb_bl61x_clock.h

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/*
 * Copyright (c) 2025-2026 MASSDRIVER EI (massdriver.space)
 *
 * SPDX-License-Identifier: Apache-2.0
 */
 
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_BFLB_BL61X_CLOCK_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_BFLB_BL61X_CLOCK_H_
 
#include "bflb_clock_common.h"


#define BL61X_CLKID_CLK_ROOT    BFLB_CLKID_CLK_ROOT
#define BL61X_CLKID_CLK_RC32M   BFLB_CLKID_CLK_RC32M
#define BL61X_CLKID_CLK_CRYSTAL BFLB_CLKID_CLK_CRYSTAL
#define BL61X_CLKID_CLK_BCLK    BFLB_CLKID_CLK_BCLK
#define BL61X_CLKID_CLK_F32K    BFLB_CLKID_CLK_F32K
#define BL61X_CLKID_CLK_XTAL32K BFLB_CLKID_CLK_XTAL32K
#define BL61X_CLKID_CLK_RC32K   BFLB_CLKID_CLK_RC32K
#define BL61X_CLKID_CLK_WIFIPLL BFLB_CLKID_CLK_PRIVATE
#define BL61X_CLKID_CLK_AUPLL   (BFLB_CLKID_CLK_PRIVATE + 1)
#define BL61X_CLKID_CLK_160M    (BFLB_CLKID_CLK_PRIVATE + 2)

#define BL61X_AUPLL_ID_DIV2     0
#define BL61X_AUPLL_ID_DIV1     1
#define BL61X_WIFIPLL_ID_DIV3_4 2
#define BL61X_WIFIPLL_ID_DIV1   3

#define BL61X_WIFIPLL_TOP_FREQ  (DT_FREQ_M(320))

#define BL61X_AUPLL_TOP_FREQ    (DT_FREQ_M(1))

#define BL61X_WIFIPLL_TOP_FREQ_OC1      (DT_FREQ_M(480))

#define BL61X_WIFIPLL_TOP_FREQ_OC2      (DT_FREQ_M(640))
 
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_BFLB_BL61X_CLOCK_H_ */