Zephyr Project API 4.2.99
A Scalable Open Source RTOS
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bflb_bl61x_clock.h File Reference

Go to the source code of this file.

Macros

#define BL61X_CLKID_CLK_ROOT   BFLB_CLKID_CLK_ROOT
 
#define BL61X_CLKID_CLK_RC32M   BFLB_CLKID_CLK_RC32M
 
#define BL61X_CLKID_CLK_CRYSTAL   BFLB_CLKID_CLK_CRYSTAL
 
#define BL61X_CLKID_CLK_BCLK   BFLB_CLKID_CLK_BCLK
 
#define BL61X_CLKID_CLK_WIFIPLL   4
 
#define BL61X_CLKID_CLK_AUPLL   5
 
#define BL61X_AUPLL_DIV2   0
 
#define BL61X_AUPLL_DIV1   1
 
#define BL61X_WIFIPLL_240MHz   2
 
#define BL61X_WIFIPLL_320MHz   3
 
#define BL61X_WIFIPLL_OC_360MHz   (2 | 0x10)
 
#define BL61X_WIFIPLL_OC_480MHz   (3 | 0x10)
 

Macro Definition Documentation

◆ BL61X_AUPLL_DIV1

#define BL61X_AUPLL_DIV1   1

◆ BL61X_AUPLL_DIV2

#define BL61X_AUPLL_DIV2   0

◆ BL61X_CLKID_CLK_AUPLL

#define BL61X_CLKID_CLK_AUPLL   5

◆ BL61X_CLKID_CLK_BCLK

#define BL61X_CLKID_CLK_BCLK   BFLB_CLKID_CLK_BCLK

◆ BL61X_CLKID_CLK_CRYSTAL

#define BL61X_CLKID_CLK_CRYSTAL   BFLB_CLKID_CLK_CRYSTAL

◆ BL61X_CLKID_CLK_RC32M

#define BL61X_CLKID_CLK_RC32M   BFLB_CLKID_CLK_RC32M

◆ BL61X_CLKID_CLK_ROOT

#define BL61X_CLKID_CLK_ROOT   BFLB_CLKID_CLK_ROOT

◆ BL61X_CLKID_CLK_WIFIPLL

#define BL61X_CLKID_CLK_WIFIPLL   4

◆ BL61X_WIFIPLL_240MHz

#define BL61X_WIFIPLL_240MHz   2

◆ BL61X_WIFIPLL_320MHz

#define BL61X_WIFIPLL_320MHz   3

◆ BL61X_WIFIPLL_OC_360MHz

#define BL61X_WIFIPLL_OC_360MHz   (2 | 0x10)

◆ BL61X_WIFIPLL_OC_480MHz

#define BL61X_WIFIPLL_OC_480MHz   (3 | 0x10)