Go to the source code of this file.
◆ BL61X_AUPLL_DIV1
#define BL61X_AUPLL_DIV1 1 |
◆ BL61X_AUPLL_DIV2
#define BL61X_AUPLL_DIV2 0 |
◆ BL61X_CLKID_CLK_AUPLL
#define BL61X_CLKID_CLK_AUPLL 5 |
◆ BL61X_CLKID_CLK_BCLK
◆ BL61X_CLKID_CLK_CRYSTAL
◆ BL61X_CLKID_CLK_RC32M
◆ BL61X_CLKID_CLK_ROOT
◆ BL61X_CLKID_CLK_WIFIPLL
#define BL61X_CLKID_CLK_WIFIPLL 4 |
◆ BL61X_WIFIPLL_240MHz
#define BL61X_WIFIPLL_240MHz 2 |
◆ BL61X_WIFIPLL_320MHz
#define BL61X_WIFIPLL_320MHz 3 |
◆ BL61X_WIFIPLL_OC_360MHz
#define BL61X_WIFIPLL_OC_360MHz (2 | 0x10) |
◆ BL61X_WIFIPLL_OC_480MHz
#define BL61X_WIFIPLL_OC_480MHz (3 | 0x10) |