Zephyr Project API 4.4.99
A Scalable Open Source RTOS
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cache.h
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1/*
2 * Copyright (c) 2015 Wind River Systems, Inc.
3 * Copyright (c) 2022 Carlo Caione <ccaione@baylibre.com>
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8#ifndef ZEPHYR_INCLUDE_CACHE_H_
9#define ZEPHYR_INCLUDE_CACHE_H_
10
15
16#include <zephyr/kernel.h>
17#include <zephyr/arch/cpu.h>
18#include <zephyr/debug/sparse.h>
19
20#ifdef __cplusplus
21extern "C" {
22#endif
23
24#if defined(CONFIG_EXTERNAL_CACHE)
26
27#elif defined(CONFIG_ARCH_CACHE)
28#include <zephyr/arch/cache.h>
29
30#elif defined(CONFIG_SOC_CACHE)
31#include <soc_cache.h>
32
33#endif
34
42
50{
51#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_DCACHE)
53#endif
54}
55
63{
64#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_DCACHE)
66#endif
67}
68
76{
77#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_ICACHE)
79#endif
80}
81
89{
90#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_ICACHE)
92#endif
93}
94
105{
106#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_DCACHE)
107 return cache_data_flush_all();
108#endif
109 return -ENOTSUP;
110}
111
122{
123#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_ICACHE)
124 return cache_instr_flush_all();
125#endif
126 return -ENOTSUP;
127}
128
139{
140#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_DCACHE)
141 return cache_data_invd_all();
142#endif
143 return -ENOTSUP;
144}
145
156{
157#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_ICACHE)
158 return cache_instr_invd_all();
159#endif
160 return -ENOTSUP;
161}
162
173{
174#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_DCACHE)
176#endif
177 return -ENOTSUP;
178}
179
190{
191#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_ICACHE)
193#endif
194 return -ENOTSUP;
195}
196
216__syscall_always_inline int sys_cache_data_flush_range(void *addr, size_t size);
217
218static ALWAYS_INLINE int z_impl_sys_cache_data_flush_range(void *addr, size_t size)
219{
220#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_DCACHE)
221 return cache_data_flush_range(addr, size);
222#endif
223 ARG_UNUSED(addr);
224 ARG_UNUSED(size);
225
226 return -ENOTSUP;
227}
228
248static ALWAYS_INLINE int sys_cache_instr_flush_range(void *addr, size_t size)
249{
250#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_ICACHE)
251 return cache_instr_flush_range(addr, size);
252#endif
253 ARG_UNUSED(addr);
254 ARG_UNUSED(size);
255
256 return -ENOTSUP;
257}
258
279__syscall_always_inline int sys_cache_data_invd_range(void *addr, size_t size);
280
281static ALWAYS_INLINE int z_impl_sys_cache_data_invd_range(void *addr, size_t size)
282{
283#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_DCACHE)
284 return cache_data_invd_range(addr, size);
285#endif
286 ARG_UNUSED(addr);
287 ARG_UNUSED(size);
288
289 return -ENOTSUP;
290}
291
312static ALWAYS_INLINE int sys_cache_instr_invd_range(void *addr, size_t size)
313{
314#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_ICACHE)
315 return cache_instr_invd_range(addr, size);
316#endif
317 ARG_UNUSED(addr);
318 ARG_UNUSED(size);
319
320 return -ENOTSUP;
321}
322
343__syscall_always_inline int sys_cache_data_flush_and_invd_range(void *addr, size_t size);
344
345static ALWAYS_INLINE int z_impl_sys_cache_data_flush_and_invd_range(void *addr, size_t size)
346{
347#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_DCACHE)
348 return cache_data_flush_and_invd_range(addr, size);
349#endif
350 ARG_UNUSED(addr);
351 ARG_UNUSED(size);
352
353 return -ENOTSUP;
354}
355
376static ALWAYS_INLINE int sys_cache_instr_flush_and_invd_range(void *addr, size_t size)
377{
378#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_ICACHE)
379 return cache_instr_flush_and_invd_range(addr, size);
380#endif
381 ARG_UNUSED(addr);
382 ARG_UNUSED(size);
383
384 return -ENOTSUP;
385}
386
403{
404#ifdef CONFIG_DCACHE_LINE_SIZE_DETECT
405 size_t dcache_line_size = cache_data_line_size_get();
406
407 __ASSERT(dcache_line_size > 0);
408 __ASSERT(dcache_line_size == CONFIG_DCACHE_LINE_SIZE);
409 return dcache_line_size;
410#elif defined(CONFIG_DCACHE)
411 return CONFIG_DCACHE_LINE_SIZE;
412#else
413 return 0;
414#endif
415}
416
433{
434#ifdef CONFIG_ICACHE_LINE_SIZE_DETECT
435 size_t icache_line_size = cache_instr_line_size_get();
436
437 __ASSERT(icache_line_size > 0);
438 __ASSERT(icache_line_size == CONFIG_ICACHE_LINE_SIZE);
439 return icache_line_size;
440#elif defined(CONFIG_ICACHE)
441 return CONFIG_ICACHE_LINE_SIZE;
442#else
443 return 0;
444#endif
445}
446
461{
462#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_CACHE_HAS_MIRRORED_MEMORY_REGIONS)
463 return cache_is_ptr_cached(ptr);
464#else
465 ARG_UNUSED(ptr);
466
467 return false;
468#endif
469}
470
485{
486#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_CACHE_HAS_MIRRORED_MEMORY_REGIONS)
487 return cache_is_ptr_uncached(ptr);
488#else
489 ARG_UNUSED(ptr);
490
491 return false;
492#endif
493}
494
513static ALWAYS_INLINE void __sparse_cache *sys_cache_cached_ptr_get(void *ptr)
514{
515#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_CACHE_HAS_MIRRORED_MEMORY_REGIONS)
516 return cache_cached_ptr(ptr);
517#else
518 return (__sparse_force void __sparse_cache *)ptr;
519#endif
520}
521
538static ALWAYS_INLINE void *sys_cache_uncached_ptr_get(void __sparse_cache *ptr)
539{
540#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_CACHE_HAS_MIRRORED_MEMORY_REGIONS)
541 return cache_uncached_ptr(ptr);
542#else
543 return (__sparse_force void *)ptr;
544#endif
545}
546
547
548#ifdef CONFIG_LIBMETAL
549static ALWAYS_INLINE void sys_cache_flush(void *addr, size_t size)
550{
551 sys_cache_data_flush_range(addr, size);
552}
553#endif
554
555#if defined(CONFIG_CACHE_CAN_SAY_MEM_COHERENCE) || defined(__DOXYGEN__)
574{
575 return cache_is_mem_coherent(ptr);
576}
577#endif /* CONFIG_CACHE_CAN_SAY_MEM_COHERENCE */
578
579#include <zephyr/syscalls/cache.h>
580#ifdef __cplusplus
581}
582#endif
583
587
588#endif /* ZEPHYR_INCLUDE_CACHE_H_ */
Public APIs for architectural cache controller drivers.
Main header file for external cache controller driver API.
#define cache_uncached_ptr(ptr)
Definition cache.h:351
#define cache_instr_invd_all
Definition cache.h:229
#define cache_cached_ptr(ptr)
Definition cache.h:348
#define cache_instr_disable
Definition cache.h:203
#define cache_is_ptr_uncached(ptr)
Definition cache.h:345
#define cache_instr_flush_all
Definition cache.h:216
#define cache_data_flush_and_invd_range(addr, size)
Definition cache.h:159
#define cache_instr_invd_range(addr, size)
Definition cache.h:289
#define cache_instr_flush_and_invd_all
Definition cache.h:242
#define cache_instr_enable
Definition cache.h:194
#define cache_instr_flush_range(addr, size)
Definition cache.h:265
#define cache_data_invd_range(addr, size)
Definition cache.h:134
#define cache_instr_flush_and_invd_range(addr, size)
Definition cache.h:313
#define cache_data_invd_all
Definition cache.h:74
#define cache_is_mem_coherent(ptr)
Definition cache.h:358
#define cache_is_ptr_cached(ptr)
Definition cache.h:342
#define cache_data_flush_range(addr, size)
Definition cache.h:110
#define cache_data_flush_and_invd_all
Definition cache.h:87
#define cache_data_flush_all
Definition cache.h:61
#define cache_data_enable
Definition cache.h:39
#define cache_instr_line_size_get
Definition cache.h:334
#define cache_data_disable
Definition cache.h:48
#define cache_data_line_size_get
Definition cache.h:179
static ALWAYS_INLINE bool sys_cache_is_ptr_cached(void *ptr)
Test if a pointer is in cached region.
Definition cache.h:460
static ALWAYS_INLINE void * sys_cache_uncached_ptr_get(void *ptr)
Return uncached pointer to a RAM address.
Definition cache.h:538
static ALWAYS_INLINE bool sys_cache_is_mem_coherent(void *ptr)
Detect memory coherence type.
Definition cache.h:573
static ALWAYS_INLINE int sys_cache_data_flush_all(void)
Flush the d-cache.
Definition cache.h:104
static ALWAYS_INLINE int sys_cache_instr_flush_and_invd_all(void)
Flush and Invalidate the i-cache.
Definition cache.h:189
static ALWAYS_INLINE size_t sys_cache_instr_line_size_get(void)
Get the i-cache line size.
Definition cache.h:432
static ALWAYS_INLINE void sys_cache_instr_disable(void)
Disable the i-cache.
Definition cache.h:88
int sys_cache_data_flush_and_invd_range(void *addr, size_t size)
Flush and Invalidate an address range in the d-cache.
int sys_cache_data_invd_range(void *addr, size_t size)
Invalidate an address range in the d-cache.
static ALWAYS_INLINE int sys_cache_instr_flush_range(void *addr, size_t size)
Flush an address range in the i-cache.
Definition cache.h:248
static ALWAYS_INLINE int sys_cache_instr_flush_all(void)
Flush the i-cache.
Definition cache.h:121
static ALWAYS_INLINE size_t sys_cache_data_line_size_get(void)
Get the d-cache line size.
Definition cache.h:402
int sys_cache_data_flush_range(void *addr, size_t size)
Flush an address range in the d-cache.
static ALWAYS_INLINE int sys_cache_instr_flush_and_invd_range(void *addr, size_t size)
Flush and Invalidate an address range in the i-cache.
Definition cache.h:376
static ALWAYS_INLINE void * sys_cache_cached_ptr_get(void *ptr)
Return cached pointer to a RAM address.
Definition cache.h:513
static ALWAYS_INLINE void sys_cache_data_disable(void)
Disable the d-cache.
Definition cache.h:62
static ALWAYS_INLINE int sys_cache_instr_invd_range(void *addr, size_t size)
Invalidate an address range in the i-cache.
Definition cache.h:312
static ALWAYS_INLINE void sys_cache_data_enable(void)
Enable the d-cache.
Definition cache.h:49
static ALWAYS_INLINE void sys_cache_instr_enable(void)
Enable the i-cache.
Definition cache.h:75
static ALWAYS_INLINE int sys_cache_data_invd_all(void)
Invalidate the d-cache.
Definition cache.h:138
static ALWAYS_INLINE bool sys_cache_is_ptr_uncached(void *ptr)
Test if a pointer is in un-cached region.
Definition cache.h:484
static ALWAYS_INLINE int sys_cache_data_flush_and_invd_all(void)
Flush and Invalidate the d-cache.
Definition cache.h:172
static ALWAYS_INLINE int sys_cache_instr_invd_all(void)
Invalidate the i-cache.
Definition cache.h:155
#define ENOTSUP
Unsupported value.
Definition errno.h:115
#define ALWAYS_INLINE
Definition common.h:180
Public kernel APIs.