Zephyr Project API 4.4.99
A Scalable Open Source RTOS
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cache.h
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1/*
2 * Copyright (c) 2015 Wind River Systems, Inc.
3 * Copyright (c) 2022 Carlo Caione <ccaione@baylibre.com>
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8#ifndef ZEPHYR_INCLUDE_CACHE_H_
9#define ZEPHYR_INCLUDE_CACHE_H_
10
15
16#include <zephyr/kernel.h>
17#include <zephyr/arch/cpu.h>
18#include <zephyr/debug/sparse.h>
19
20#ifdef __cplusplus
21extern "C" {
22#endif
23
24#if defined(CONFIG_EXTERNAL_CACHE)
26
27#elif defined(CONFIG_ARCH_CACHE)
28#include <zephyr/arch/cache.h>
29
30#elif defined(CONFIG_SOC_CACHE)
31#include <soc_cache.h>
32
33#endif
34
42
50{
51#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_DCACHE)
53#endif
54}
55
63{
64#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_DCACHE)
66#endif
67}
68
76{
77#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_ICACHE)
79#endif
80}
81
89{
90#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_ICACHE)
92#endif
93}
94
104{
105#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_DCACHE)
106 return cache_data_flush_all();
107#endif
108 return -ENOTSUP;
109}
110
120{
121#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_ICACHE)
122 return cache_instr_flush_all();
123#endif
124 return -ENOTSUP;
125}
126
136{
137#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_DCACHE)
138 return cache_data_invd_all();
139#endif
140 return -ENOTSUP;
141}
142
152{
153#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_ICACHE)
154 return cache_instr_invd_all();
155#endif
156 return -ENOTSUP;
157}
158
168{
169#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_DCACHE)
171#endif
172 return -ENOTSUP;
173}
174
184{
185#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_ICACHE)
187#endif
188 return -ENOTSUP;
189}
190
209__syscall_always_inline int sys_cache_data_flush_range(void *addr, size_t size);
210
211static ALWAYS_INLINE int z_impl_sys_cache_data_flush_range(void *addr, size_t size)
212{
213#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_DCACHE)
214 return cache_data_flush_range(addr, size);
215#endif
216 ARG_UNUSED(addr);
217 ARG_UNUSED(size);
218
219 return -ENOTSUP;
220}
221
240static ALWAYS_INLINE int sys_cache_instr_flush_range(void *addr, size_t size)
241{
242#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_ICACHE)
243 return cache_instr_flush_range(addr, size);
244#endif
245 ARG_UNUSED(addr);
246 ARG_UNUSED(size);
247
248 return -ENOTSUP;
249}
250
270__syscall_always_inline int sys_cache_data_invd_range(void *addr, size_t size);
271
272static ALWAYS_INLINE int z_impl_sys_cache_data_invd_range(void *addr, size_t size)
273{
274#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_DCACHE)
275 return cache_data_invd_range(addr, size);
276#endif
277 ARG_UNUSED(addr);
278 ARG_UNUSED(size);
279
280 return -ENOTSUP;
281}
282
302static ALWAYS_INLINE int sys_cache_instr_invd_range(void *addr, size_t size)
303{
304#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_ICACHE)
305 return cache_instr_invd_range(addr, size);
306#endif
307 ARG_UNUSED(addr);
308 ARG_UNUSED(size);
309
310 return -ENOTSUP;
311}
312
332__syscall_always_inline int sys_cache_data_flush_and_invd_range(void *addr, size_t size);
333
334static ALWAYS_INLINE int z_impl_sys_cache_data_flush_and_invd_range(void *addr, size_t size)
335{
336#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_DCACHE)
337 return cache_data_flush_and_invd_range(addr, size);
338#endif
339 ARG_UNUSED(addr);
340 ARG_UNUSED(size);
341
342 return -ENOTSUP;
343}
344
364static ALWAYS_INLINE int sys_cache_instr_flush_and_invd_range(void *addr, size_t size)
365{
366#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_ICACHE)
367 return cache_instr_flush_and_invd_range(addr, size);
368#endif
369 ARG_UNUSED(addr);
370 ARG_UNUSED(size);
371
372 return -ENOTSUP;
373}
374
391{
392#ifdef CONFIG_DCACHE_LINE_SIZE_DETECT
393 size_t dcache_line_size = cache_data_line_size_get();
394
395 __ASSERT(dcache_line_size > 0);
396 __ASSERT(dcache_line_size == CONFIG_DCACHE_LINE_SIZE);
397 return dcache_line_size;
398#elif defined(CONFIG_DCACHE)
399 return CONFIG_DCACHE_LINE_SIZE;
400#else
401 return 0;
402#endif
403}
404
421{
422#ifdef CONFIG_ICACHE_LINE_SIZE_DETECT
423 size_t icache_line_size = cache_instr_line_size_get();
424
425 __ASSERT(icache_line_size > 0);
426 __ASSERT(icache_line_size == CONFIG_ICACHE_LINE_SIZE);
427 return icache_line_size;
428#elif defined(CONFIG_ICACHE)
429 return CONFIG_ICACHE_LINE_SIZE;
430#else
431 return 0;
432#endif
433}
434
449{
450#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_CACHE_HAS_MIRRORED_MEMORY_REGIONS)
451 return cache_is_ptr_cached(ptr);
452#else
453 ARG_UNUSED(ptr);
454
455 return false;
456#endif
457}
458
473{
474#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_CACHE_HAS_MIRRORED_MEMORY_REGIONS)
475 return cache_is_ptr_uncached(ptr);
476#else
477 ARG_UNUSED(ptr);
478
479 return false;
480#endif
481}
482
501static ALWAYS_INLINE void __sparse_cache *sys_cache_cached_ptr_get(void *ptr)
502{
503#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_CACHE_HAS_MIRRORED_MEMORY_REGIONS)
504 return cache_cached_ptr(ptr);
505#else
506 return (__sparse_force void __sparse_cache *)ptr;
507#endif
508}
509
526static ALWAYS_INLINE void *sys_cache_uncached_ptr_get(void __sparse_cache *ptr)
527{
528#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_CACHE_HAS_MIRRORED_MEMORY_REGIONS)
529 return cache_uncached_ptr(ptr);
530#else
531 return (__sparse_force void *)ptr;
532#endif
533}
534
535
536#ifdef CONFIG_LIBMETAL
537static ALWAYS_INLINE void sys_cache_flush(void *addr, size_t size)
538{
539 sys_cache_data_flush_range(addr, size);
540}
541#endif
542
543#if defined(CONFIG_CACHE_CAN_SAY_MEM_COHERENCE) || defined(__DOXYGEN__)
562{
563 return cache_is_mem_coherent(ptr);
564}
565#endif /* CONFIG_CACHE_CAN_SAY_MEM_COHERENCE */
566
567#include <zephyr/syscalls/cache.h>
568#ifdef __cplusplus
569}
570#endif
571
575
576#endif /* ZEPHYR_INCLUDE_CACHE_H_ */
Public APIs for architectural cache controller drivers.
Main header file for external cache controller driver API.
#define cache_uncached_ptr(ptr)
Definition cache.h:351
#define cache_instr_invd_all
Definition cache.h:229
#define cache_cached_ptr(ptr)
Definition cache.h:348
#define cache_instr_disable
Definition cache.h:203
#define cache_is_ptr_uncached(ptr)
Definition cache.h:345
#define cache_instr_flush_all
Definition cache.h:216
#define cache_data_flush_and_invd_range(addr, size)
Definition cache.h:159
#define cache_instr_invd_range(addr, size)
Definition cache.h:289
#define cache_instr_flush_and_invd_all
Definition cache.h:242
#define cache_instr_enable
Definition cache.h:194
#define cache_instr_flush_range(addr, size)
Definition cache.h:265
#define cache_data_invd_range(addr, size)
Definition cache.h:134
#define cache_instr_flush_and_invd_range(addr, size)
Definition cache.h:313
#define cache_data_invd_all
Definition cache.h:74
#define cache_is_mem_coherent(ptr)
Definition cache.h:358
#define cache_is_ptr_cached(ptr)
Definition cache.h:342
#define cache_data_flush_range(addr, size)
Definition cache.h:110
#define cache_data_flush_and_invd_all
Definition cache.h:87
#define cache_data_flush_all
Definition cache.h:61
#define cache_data_enable
Definition cache.h:39
#define cache_instr_line_size_get
Definition cache.h:334
#define cache_data_disable
Definition cache.h:48
#define cache_data_line_size_get
Definition cache.h:179
static ALWAYS_INLINE bool sys_cache_is_ptr_cached(void *ptr)
Test if a pointer is in cached region.
Definition cache.h:448
static ALWAYS_INLINE void * sys_cache_uncached_ptr_get(void *ptr)
Return uncached pointer to a RAM address.
Definition cache.h:526
static ALWAYS_INLINE bool sys_cache_is_mem_coherent(void *ptr)
Detect memory coherence type.
Definition cache.h:561
static ALWAYS_INLINE int sys_cache_data_flush_all(void)
Flush the d-cache.
Definition cache.h:103
static ALWAYS_INLINE int sys_cache_instr_flush_and_invd_all(void)
Flush and Invalidate the i-cache.
Definition cache.h:183
static ALWAYS_INLINE size_t sys_cache_instr_line_size_get(void)
Get the i-cache line size.
Definition cache.h:420
static ALWAYS_INLINE void sys_cache_instr_disable(void)
Disable the i-cache.
Definition cache.h:88
int sys_cache_data_flush_and_invd_range(void *addr, size_t size)
Flush and Invalidate an address range in the d-cache.
int sys_cache_data_invd_range(void *addr, size_t size)
Invalidate an address range in the d-cache.
static ALWAYS_INLINE int sys_cache_instr_flush_range(void *addr, size_t size)
Flush an address range in the i-cache.
Definition cache.h:240
static ALWAYS_INLINE int sys_cache_instr_flush_all(void)
Flush the i-cache.
Definition cache.h:119
static ALWAYS_INLINE size_t sys_cache_data_line_size_get(void)
Get the d-cache line size.
Definition cache.h:390
int sys_cache_data_flush_range(void *addr, size_t size)
Flush an address range in the d-cache.
static ALWAYS_INLINE int sys_cache_instr_flush_and_invd_range(void *addr, size_t size)
Flush and Invalidate an address range in the i-cache.
Definition cache.h:364
static ALWAYS_INLINE void * sys_cache_cached_ptr_get(void *ptr)
Return cached pointer to a RAM address.
Definition cache.h:501
static ALWAYS_INLINE void sys_cache_data_disable(void)
Disable the d-cache.
Definition cache.h:62
static ALWAYS_INLINE int sys_cache_instr_invd_range(void *addr, size_t size)
Invalidate an address range in the i-cache.
Definition cache.h:302
static ALWAYS_INLINE void sys_cache_data_enable(void)
Enable the d-cache.
Definition cache.h:49
static ALWAYS_INLINE void sys_cache_instr_enable(void)
Enable the i-cache.
Definition cache.h:75
static ALWAYS_INLINE int sys_cache_data_invd_all(void)
Invalidate the d-cache.
Definition cache.h:135
static ALWAYS_INLINE bool sys_cache_is_ptr_uncached(void *ptr)
Test if a pointer is in un-cached region.
Definition cache.h:472
static ALWAYS_INLINE int sys_cache_data_flush_and_invd_all(void)
Flush and Invalidate the d-cache.
Definition cache.h:167
static ALWAYS_INLINE int sys_cache_instr_invd_all(void)
Invalidate the i-cache.
Definition cache.h:151
#define ENOTSUP
Unsupported value.
Definition errno.h:115
#define ALWAYS_INLINE
Definition common.h:186
Public kernel APIs.