Zephyr Project API 4.2.99
A Scalable Open Source RTOS
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cache.h
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1/*
2 * Copyright (c) 2015 Wind River Systems, Inc.
3 * Copyright (c) 2022 Carlo Caione <ccaione@baylibre.com>
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8#ifndef ZEPHYR_INCLUDE_CACHE_H_
9#define ZEPHYR_INCLUDE_CACHE_H_
10
16#include <zephyr/kernel.h>
17#include <zephyr/arch/cpu.h>
18#include <zephyr/debug/sparse.h>
19
20#ifdef __cplusplus
21extern "C" {
22#endif
23
24#if defined(CONFIG_EXTERNAL_CACHE)
26
27#elif defined(CONFIG_ARCH_CACHE)
28#include <zephyr/arch/cache.h>
29
30#endif
31
45{
46#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_DCACHE)
48#endif
49}
50
58{
59#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_DCACHE)
61#endif
62}
63
71{
72#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_ICACHE)
74#endif
75}
76
84{
85#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_ICACHE)
87#endif
88}
89
100{
101#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_DCACHE)
102 return cache_data_flush_all();
103#endif
104 return -ENOTSUP;
105}
106
117{
118#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_ICACHE)
119 return cache_instr_flush_all();
120#endif
121 return -ENOTSUP;
122}
123
134{
135#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_DCACHE)
136 return cache_data_invd_all();
137#endif
138 return -ENOTSUP;
139}
140
151{
152#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_ICACHE)
153 return cache_instr_invd_all();
154#endif
155 return -ENOTSUP;
156}
157
168{
169#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_DCACHE)
171#endif
172 return -ENOTSUP;
173}
174
185{
186#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_ICACHE)
188#endif
189 return -ENOTSUP;
190}
191
211__syscall_always_inline int sys_cache_data_flush_range(void *addr, size_t size);
212
213static ALWAYS_INLINE int z_impl_sys_cache_data_flush_range(void *addr, size_t size)
214{
215#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_DCACHE)
216 return cache_data_flush_range(addr, size);
217#endif
218 ARG_UNUSED(addr);
219 ARG_UNUSED(size);
220
221 return -ENOTSUP;
222}
223
243static ALWAYS_INLINE int sys_cache_instr_flush_range(void *addr, size_t size)
244{
245#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_ICACHE)
246 return cache_instr_flush_range(addr, size);
247#endif
248 ARG_UNUSED(addr);
249 ARG_UNUSED(size);
250
251 return -ENOTSUP;
252}
253
274__syscall_always_inline int sys_cache_data_invd_range(void *addr, size_t size);
275
276static ALWAYS_INLINE int z_impl_sys_cache_data_invd_range(void *addr, size_t size)
277{
278#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_DCACHE)
279 return cache_data_invd_range(addr, size);
280#endif
281 ARG_UNUSED(addr);
282 ARG_UNUSED(size);
283
284 return -ENOTSUP;
285}
286
307static ALWAYS_INLINE int sys_cache_instr_invd_range(void *addr, size_t size)
308{
309#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_ICACHE)
310 return cache_instr_invd_range(addr, size);
311#endif
312 ARG_UNUSED(addr);
313 ARG_UNUSED(size);
314
315 return -ENOTSUP;
316}
317
338__syscall_always_inline int sys_cache_data_flush_and_invd_range(void *addr, size_t size);
339
340static ALWAYS_INLINE int z_impl_sys_cache_data_flush_and_invd_range(void *addr, size_t size)
341{
342#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_DCACHE)
343 return cache_data_flush_and_invd_range(addr, size);
344#endif
345 ARG_UNUSED(addr);
346 ARG_UNUSED(size);
347
348 return -ENOTSUP;
349}
350
371static ALWAYS_INLINE int sys_cache_instr_flush_and_invd_range(void *addr, size_t size)
372{
373#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_ICACHE)
374 return cache_instr_flush_and_invd_range(addr, size);
375#endif
376 ARG_UNUSED(addr);
377 ARG_UNUSED(size);
378
379 return -ENOTSUP;
380}
381
398{
399#ifdef CONFIG_DCACHE_LINE_SIZE_DETECT
401#elif defined(CONFIG_DCACHE_LINE_SIZE)
402 return CONFIG_DCACHE_LINE_SIZE;
403#else
404 return 0;
405#endif
406}
407
424{
425#ifdef CONFIG_ICACHE_LINE_SIZE_DETECT
427#elif defined(CONFIG_ICACHE_LINE_SIZE)
428 return CONFIG_ICACHE_LINE_SIZE;
429#else
430 return 0;
431#endif
432}
433
448{
449#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_CACHE_DOUBLEMAP)
450 return cache_is_ptr_cached(ptr);
451#else
452 ARG_UNUSED(ptr);
453
454 return false;
455#endif
456}
457
472{
473#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_CACHE_DOUBLEMAP)
474 return cache_is_ptr_uncached(ptr);
475#else
476 ARG_UNUSED(ptr);
477
478 return false;
479#endif
480}
481
500static ALWAYS_INLINE void __sparse_cache *sys_cache_cached_ptr_get(void *ptr)
501{
502#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_CACHE_DOUBLEMAP)
503 return cache_cached_ptr(ptr);
504#else
505 return (__sparse_force void __sparse_cache *)ptr;
506#endif
507}
508
525static ALWAYS_INLINE void *sys_cache_uncached_ptr_get(void __sparse_cache *ptr)
526{
527#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_CACHE_DOUBLEMAP)
528 return cache_uncached_ptr(ptr);
529#else
530 return (__sparse_force void *)ptr;
531#endif
532}
533
534
535#ifdef CONFIG_LIBMETAL
536static ALWAYS_INLINE void sys_cache_flush(void *addr, size_t size)
537{
538 sys_cache_data_flush_range(addr, size);
539}
540#endif
541
542#include <zephyr/syscalls/cache.h>
543#ifdef __cplusplus
544}
545#endif
546
551#endif /* ZEPHYR_INCLUDE_CACHE_H_ */
Public APIs for architectural cache controller drivers.
Main header file for external cache controller driver API.
#define cache_uncached_ptr(ptr)
Definition cache.h:348
#define cache_instr_invd_all
Definition cache.h:226
#define cache_cached_ptr(ptr)
Definition cache.h:345
#define cache_instr_disable
Definition cache.h:200
#define cache_is_ptr_uncached(ptr)
Definition cache.h:342
#define cache_instr_flush_all
Definition cache.h:213
#define cache_data_flush_and_invd_range(addr, size)
Definition cache.h:156
#define cache_instr_invd_range(addr, size)
Definition cache.h:286
#define cache_instr_flush_and_invd_all
Definition cache.h:239
#define cache_instr_enable
Definition cache.h:191
#define cache_instr_flush_range(addr, size)
Definition cache.h:262
#define cache_data_invd_range(addr, size)
Definition cache.h:131
#define cache_instr_flush_and_invd_range(addr, size)
Definition cache.h:310
#define cache_data_invd_all
Definition cache.h:71
#define cache_is_ptr_cached(ptr)
Definition cache.h:339
#define cache_data_flush_range(addr, size)
Definition cache.h:107
#define cache_data_flush_and_invd_all
Definition cache.h:84
#define cache_data_flush_all
Definition cache.h:58
#define cache_data_enable
Definition cache.h:36
#define cache_instr_line_size_get
Definition cache.h:331
#define cache_data_disable
Definition cache.h:45
#define cache_data_line_size_get
Definition cache.h:176
static ALWAYS_INLINE bool sys_cache_is_ptr_cached(void *ptr)
Test if a pointer is in cached region.
Definition cache.h:447
static ALWAYS_INLINE void * sys_cache_uncached_ptr_get(void *ptr)
Return uncached pointer to a RAM address.
Definition cache.h:525
static ALWAYS_INLINE int sys_cache_data_flush_all(void)
Flush the d-cache.
Definition cache.h:99
static ALWAYS_INLINE int sys_cache_instr_flush_and_invd_all(void)
Flush and Invalidate the i-cache.
Definition cache.h:184
static ALWAYS_INLINE size_t sys_cache_instr_line_size_get(void)
Get the i-cache line size.
Definition cache.h:423
static ALWAYS_INLINE void sys_cache_instr_disable(void)
Disable the i-cache.
Definition cache.h:83
int sys_cache_data_flush_and_invd_range(void *addr, size_t size)
Flush and Invalidate an address range in the d-cache.
int sys_cache_data_invd_range(void *addr, size_t size)
Invalidate an address range in the d-cache.
static ALWAYS_INLINE int sys_cache_instr_flush_range(void *addr, size_t size)
Flush an address range in the i-cache.
Definition cache.h:243
static ALWAYS_INLINE int sys_cache_instr_flush_all(void)
Flush the i-cache.
Definition cache.h:116
static ALWAYS_INLINE size_t sys_cache_data_line_size_get(void)
Get the d-cache line size.
Definition cache.h:397
int sys_cache_data_flush_range(void *addr, size_t size)
Flush an address range in the d-cache.
static ALWAYS_INLINE int sys_cache_instr_flush_and_invd_range(void *addr, size_t size)
Flush and Invalidate an address range in the i-cache.
Definition cache.h:371
static ALWAYS_INLINE void * sys_cache_cached_ptr_get(void *ptr)
Return cached pointer to a RAM address.
Definition cache.h:500
static ALWAYS_INLINE void sys_cache_data_disable(void)
Disable the d-cache.
Definition cache.h:57
static ALWAYS_INLINE int sys_cache_instr_invd_range(void *addr, size_t size)
Invalidate an address range in the i-cache.
Definition cache.h:307
static ALWAYS_INLINE void sys_cache_data_enable(void)
Enable the d-cache.
Definition cache.h:44
static ALWAYS_INLINE void sys_cache_instr_enable(void)
Enable the i-cache.
Definition cache.h:70
static ALWAYS_INLINE int sys_cache_data_invd_all(void)
Invalidate the d-cache.
Definition cache.h:133
static ALWAYS_INLINE bool sys_cache_is_ptr_uncached(void *ptr)
Test if a pointer is in un-cached region.
Definition cache.h:471
static ALWAYS_INLINE int sys_cache_data_flush_and_invd_all(void)
Flush and Invalidate the d-cache.
Definition cache.h:167
static ALWAYS_INLINE int sys_cache_instr_invd_all(void)
Invalidate the i-cache.
Definition cache.h:150
#define ENOTSUP
Unsupported value.
Definition errno.h:114
#define ALWAYS_INLINE
Definition common.h:160
Public kernel APIs.