Zephyr Project API 3.7.0
A Scalable Open Source RTOS
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cache.h
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1/*
2 * Copyright (c) 2015 Wind River Systems, Inc.
3 * Copyright (c) 2022 Carlo Caione <ccaione@baylibre.com>
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8#ifndef ZEPHYR_INCLUDE_CACHE_H_
9#define ZEPHYR_INCLUDE_CACHE_H_
10
16#include <zephyr/kernel.h>
17#include <zephyr/arch/cpu.h>
18#include <zephyr/debug/sparse.h>
19
20#ifdef __cplusplus
21extern "C" {
22#endif
23
24#if defined(CONFIG_EXTERNAL_CACHE)
26
27#elif defined(CONFIG_ARCH_CACHE)
28#include <zephyr/arch/cache.h>
29
30#endif
31
43#define _CPU DT_PATH(cpus, cpu_0)
44
54{
55#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_DCACHE)
57#endif
58}
59
67{
68#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_DCACHE)
70#endif
71}
72
80{
81#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_ICACHE)
83#endif
84}
85
93{
94#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_ICACHE)
96#endif
97}
98
109{
110#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_DCACHE)
111 return cache_data_flush_all();
112#endif
113 return -ENOTSUP;
114}
115
126{
127#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_ICACHE)
128 return cache_instr_flush_all();
129#endif
130 return -ENOTSUP;
131}
132
143{
144#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_DCACHE)
145 return cache_data_invd_all();
146#endif
147 return -ENOTSUP;
148}
149
160{
161#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_ICACHE)
162 return cache_instr_invd_all();
163#endif
164 return -ENOTSUP;
165}
166
177{
178#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_DCACHE)
180#endif
181 return -ENOTSUP;
182}
183
194{
195#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_ICACHE)
197#endif
198 return -ENOTSUP;
199}
200
220__syscall_always_inline int sys_cache_data_flush_range(void *addr, size_t size);
221
222static ALWAYS_INLINE int z_impl_sys_cache_data_flush_range(void *addr, size_t size)
223{
224#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_DCACHE)
225 return cache_data_flush_range(addr, size);
226#endif
227 ARG_UNUSED(addr);
228 ARG_UNUSED(size);
229
230 return -ENOTSUP;
231}
232
252static ALWAYS_INLINE int sys_cache_instr_flush_range(void *addr, size_t size)
253{
254#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_ICACHE)
255 return cache_instr_flush_range(addr, size);
256#endif
257 ARG_UNUSED(addr);
258 ARG_UNUSED(size);
259
260 return -ENOTSUP;
261}
262
283__syscall_always_inline int sys_cache_data_invd_range(void *addr, size_t size);
284
285static ALWAYS_INLINE int z_impl_sys_cache_data_invd_range(void *addr, size_t size)
286{
287#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_DCACHE)
288 return cache_data_invd_range(addr, size);
289#endif
290 ARG_UNUSED(addr);
291 ARG_UNUSED(size);
292
293 return -ENOTSUP;
294}
295
316static ALWAYS_INLINE int sys_cache_instr_invd_range(void *addr, size_t size)
317{
318#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_ICACHE)
319 return cache_instr_invd_range(addr, size);
320#endif
321 ARG_UNUSED(addr);
322 ARG_UNUSED(size);
323
324 return -ENOTSUP;
325}
326
347__syscall_always_inline int sys_cache_data_flush_and_invd_range(void *addr, size_t size);
348
349static ALWAYS_INLINE int z_impl_sys_cache_data_flush_and_invd_range(void *addr, size_t size)
350{
351#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_DCACHE)
352 return cache_data_flush_and_invd_range(addr, size);
353#endif
354 ARG_UNUSED(addr);
355 ARG_UNUSED(size);
356
357 return -ENOTSUP;
358}
359
380static ALWAYS_INLINE int sys_cache_instr_flush_and_invd_range(void *addr, size_t size)
381{
382#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_ICACHE)
383 return cache_instr_flush_and_invd_range(addr, size);
384#endif
385 ARG_UNUSED(addr);
386 ARG_UNUSED(size);
387
388 return -ENOTSUP;
389}
390
408{
409#ifdef CONFIG_DCACHE_LINE_SIZE_DETECT
411#elif (CONFIG_DCACHE_LINE_SIZE != 0)
412 return CONFIG_DCACHE_LINE_SIZE;
413#else
414 return DT_PROP_OR(_CPU, d_cache_line_size, 0);
415#endif
416}
417
435{
436#ifdef CONFIG_ICACHE_LINE_SIZE_DETECT
438#elif (CONFIG_ICACHE_LINE_SIZE != 0)
439 return CONFIG_ICACHE_LINE_SIZE;
440#else
441 return DT_PROP_OR(_CPU, i_cache_line_size, 0);
442#endif
443}
444
459{
460#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_CACHE_DOUBLEMAP)
461 return cache_is_ptr_cached(ptr);
462#else
463 ARG_UNUSED(ptr);
464
465 return false;
466#endif
467}
468
483{
484#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_CACHE_DOUBLEMAP)
486#else
487 ARG_UNUSED(ptr);
488
489 return false;
490#endif
491}
492
511static ALWAYS_INLINE void __sparse_cache *sys_cache_cached_ptr_get(void *ptr)
512{
513#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_CACHE_DOUBLEMAP)
514 return cache_cached_ptr(ptr);
515#else
516 return (__sparse_force void __sparse_cache *)ptr;
517#endif
518}
519
536static ALWAYS_INLINE void *sys_cache_uncached_ptr_get(void __sparse_cache *ptr)
537{
538#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_CACHE_DOUBLEMAP)
539 return cache_uncached_ptr(ptr);
540#else
541 return (__sparse_force void *)ptr;
542#endif
543}
544
545
546#ifdef CONFIG_LIBMETAL
547static ALWAYS_INLINE void sys_cache_flush(void *addr, size_t size)
548{
549 sys_cache_data_flush_range(addr, size);
550}
551#endif
552
553#include <zephyr/syscalls/cache.h>
554#ifdef __cplusplus
555}
556#endif
557
562#endif /* ZEPHYR_INCLUDE_CACHE_H_ */
Public APIs for architectural cache controller drivers.
#define ALWAYS_INLINE
Definition common.h:129
Public APIs for external cache controller drivers.
#define cache_uncached_ptr(ptr)
Definition cache.h:349
#define cache_instr_invd_all
Definition cache.h:227
#define cache_cached_ptr(ptr)
Definition cache.h:346
#define cache_instr_disable
Definition cache.h:201
#define cache_is_ptr_uncached(ptr)
Definition cache.h:343
#define cache_instr_flush_all
Definition cache.h:214
#define cache_data_flush_and_invd_range(addr, size)
Definition cache.h:157
#define cache_instr_invd_range(addr, size)
Definition cache.h:287
#define cache_instr_flush_and_invd_all
Definition cache.h:240
#define cache_instr_enable
Definition cache.h:192
#define cache_instr_flush_range(addr, size)
Definition cache.h:263
#define cache_data_invd_range(addr, size)
Definition cache.h:132
#define cache_instr_flush_and_invd_range(addr, size)
Definition cache.h:311
#define cache_data_invd_all
Definition cache.h:72
#define cache_is_ptr_cached(ptr)
Definition cache.h:340
#define cache_data_flush_range(addr, size)
Definition cache.h:108
#define cache_data_flush_and_invd_all
Definition cache.h:85
#define cache_data_flush_all
Definition cache.h:59
#define cache_data_enable
Definition cache.h:37
#define cache_instr_line_size_get
Definition cache.h:332
#define cache_data_disable
Definition cache.h:46
#define cache_data_line_size_get
Definition cache.h:177
static ALWAYS_INLINE bool sys_cache_is_ptr_cached(void *ptr)
Test if a pointer is in cached region.
Definition cache.h:458
static ALWAYS_INLINE int sys_cache_data_flush_all(void)
Flush the d-cache.
Definition cache.h:108
static ALWAYS_INLINE int sys_cache_instr_flush_and_invd_all(void)
Flush and Invalidate the i-cache.
Definition cache.h:193
static ALWAYS_INLINE size_t sys_cache_instr_line_size_get(void)
Get the i-cache line size.
Definition cache.h:434
static ALWAYS_INLINE void sys_cache_instr_disable(void)
Disable the i-cache.
Definition cache.h:92
int sys_cache_data_flush_and_invd_range(void *addr, size_t size)
Flush and Invalidate an address range in the d-cache.
int sys_cache_data_invd_range(void *addr, size_t size)
Invalidate an address range in the d-cache.
static ALWAYS_INLINE int sys_cache_instr_flush_range(void *addr, size_t size)
Flush an address range in the i-cache.
Definition cache.h:252
static ALWAYS_INLINE int sys_cache_instr_flush_all(void)
Flush the i-cache.
Definition cache.h:125
static ALWAYS_INLINE size_t sys_cache_data_line_size_get(void)
Get the d-cache line size.
Definition cache.h:407
int sys_cache_data_flush_range(void *addr, size_t size)
Flush an address range in the d-cache.
static ALWAYS_INLINE int sys_cache_instr_flush_and_invd_range(void *addr, size_t size)
Flush and Invalidate an address range in the i-cache.
Definition cache.h:380
static ALWAYS_INLINE void sys_cache_data_disable(void)
Disable the d-cache.
Definition cache.h:66
static ALWAYS_INLINE int sys_cache_instr_invd_range(void *addr, size_t size)
Invalidate an address range in the i-cache.
Definition cache.h:316
static ALWAYS_INLINE void * sys_cache_uncached_ptr_get(void __sparse_cache *ptr)
Return uncached pointer to a RAM address.
Definition cache.h:536
static ALWAYS_INLINE void sys_cache_data_enable(void)
Enable the d-cache.
Definition cache.h:53
static ALWAYS_INLINE void sys_cache_instr_enable(void)
Enable the i-cache.
Definition cache.h:79
static ALWAYS_INLINE int sys_cache_data_invd_all(void)
Invalidate the d-cache.
Definition cache.h:142
static ALWAYS_INLINE bool sys_cache_is_ptr_uncached(void *ptr)
Test if a pointer is in un-cached region.
Definition cache.h:482
static ALWAYS_INLINE int sys_cache_data_flush_and_invd_all(void)
Flush and Invalidate the d-cache.
Definition cache.h:176
static ALWAYS_INLINE int sys_cache_instr_invd_all(void)
Invalidate the i-cache.
Definition cache.h:159
static ALWAYS_INLINE void __sparse_cache * sys_cache_cached_ptr_get(void *ptr)
Return cached pointer to a RAM address.
Definition cache.h:511
#define DT_PROP_OR(node_id, prop, default_value)
Like DT_PROP(), but with a fallback to default_value.
Definition devicetree.h:825
#define ENOTSUP
Unsupported value.
Definition errno.h:114
Public kernel APIs.
void * ptr
Definition printk.c:177