Zephyr Project API 3.7.0
A Scalable Open Source RTOS
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csr.h
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1/*
2 * Copyright (c) 2020 Michael Schaffner
3 * Copyright (c) 2020 BayLibre, SAS
4 *
5 * SPDX-License-Identifier: SHL-0.51
6 * SPDX-License-Identifier: Apache-2.0
7 */
8
9#ifndef CSR_H_
10#define CSR_H_
11
12#define MSTATUS_UIE 0x00000001
13#define MSTATUS_SIE 0x00000002
14#define MSTATUS_HIE 0x00000004
15#define MSTATUS_MIE 0x00000008
16#define MSTATUS_UPIE 0x00000010
17#define MSTATUS_SPIE 0x00000020
18#define MSTATUS_HPIE 0x00000040
19#define MSTATUS_MPIE 0x00000080
20#define MSTATUS_SPP 0x00000100
21#define MSTATUS_HPP 0x00000600
22#define MSTATUS_MPP 0x00001800
23#define MSTATUS_FS 0x00006000
24#define MSTATUS_XS 0x00018000
25#define MSTATUS_MPRV 0x00020000
26#define MSTATUS_SUM 0x00040000
27#define MSTATUS_MXR 0x00080000
28#define MSTATUS_TVM 0x00100000
29#define MSTATUS_TW 0x00200000
30#define MSTATUS_TSR 0x00400000
31#define MSTATUS32_SD 0x80000000
32#define MSTATUS_UXL 0x0000000300000000
33#define MSTATUS_SXL 0x0000000C00000000
34#define MSTATUS64_SD 0x8000000000000000
35
36#define SSTATUS_UIE 0x00000001
37#define SSTATUS_SIE 0x00000002
38#define SSTATUS_UPIE 0x00000010
39#define SSTATUS_SPIE 0x00000020
40#define SSTATUS_SPP 0x00000100
41#define SSTATUS_FS 0x00006000
42#define SSTATUS_XS 0x00018000
43#define SSTATUS_SUM 0x00040000
44#define SSTATUS_MXR 0x00080000
45#define SSTATUS32_SD 0x80000000
46#define SSTATUS_UXL 0x0000000300000000
47#define SSTATUS64_SD 0x8000000000000000
48
49#define DCSR_XDEBUGVER (3U<<30)
50#define DCSR_NDRESET (1<<29)
51#define DCSR_FULLRESET (1<<28)
52#define DCSR_EBREAKM (1<<15)
53#define DCSR_EBREAKH (1<<14)
54#define DCSR_EBREAKS (1<<13)
55#define DCSR_EBREAKU (1<<12)
56#define DCSR_STOPCYCLE (1<<10)
57#define DCSR_STOPTIME (1<<9)
58#define DCSR_CAUSE (7<<6)
59#define DCSR_DEBUGINT (1<<5)
60#define DCSR_HALT (1<<3)
61#define DCSR_STEP (1<<2)
62#define DCSR_PRV (3<<0)
63
64#define DCSR_CAUSE_NONE 0
65#define DCSR_CAUSE_SWBP 1
66#define DCSR_CAUSE_HWBP 2
67#define DCSR_CAUSE_DEBUGINT 3
68#define DCSR_CAUSE_STEP 4
69#define DCSR_CAUSE_HALT 5
70
71#define MCONTROL_TYPE(xlen) (0xfULL<<((xlen)-4))
72#define MCONTROL_DMODE(xlen) (1ULL<<((xlen)-5))
73#define MCONTROL_MASKMAX(xlen) (0x3fULL<<((xlen)-11))
74
75#define MCONTROL_SELECT (1<<19)
76#define MCONTROL_TIMING (1<<18)
77#define MCONTROL_ACTION (0x3f<<12)
78#define MCONTROL_CHAIN (1<<11)
79#define MCONTROL_MATCH (0xf<<7)
80#define MCONTROL_M (1<<6)
81#define MCONTROL_H (1<<5)
82#define MCONTROL_S (1<<4)
83#define MCONTROL_U (1<<3)
84#define MCONTROL_EXECUTE (1<<2)
85#define MCONTROL_STORE (1<<1)
86#define MCONTROL_LOAD (1<<0)
87
88#define MCONTROL_TYPE_NONE 0
89#define MCONTROL_TYPE_MATCH 2
90
91#define MCONTROL_ACTION_DEBUG_EXCEPTION 0
92#define MCONTROL_ACTION_DEBUG_MODE 1
93#define MCONTROL_ACTION_TRACE_START 2
94#define MCONTROL_ACTION_TRACE_STOP 3
95#define MCONTROL_ACTION_TRACE_EMIT 4
96
97#define MCONTROL_MATCH_EQUAL 0
98#define MCONTROL_MATCH_NAPOT 1
99#define MCONTROL_MATCH_GE 2
100#define MCONTROL_MATCH_LT 3
101#define MCONTROL_MATCH_MASK_LOW 4
102#define MCONTROL_MATCH_MASK_HIGH 5
103
104#define MIP_SSIP (1 << IRQ_S_SOFT)
105#define MIP_HSIP (1 << IRQ_H_SOFT)
106#define MIP_MSIP (1 << IRQ_M_SOFT)
107#define MIP_STIP (1 << IRQ_S_TIMER)
108#define MIP_HTIP (1 << IRQ_H_TIMER)
109#define MIP_MTIP (1 << IRQ_M_TIMER)
110#define MIP_SEIP (1 << IRQ_S_EXT)
111#define MIP_HEIP (1 << IRQ_H_EXT)
112#define MIP_MEIP (1 << IRQ_M_EXT)
113
114#define SIP_SSIP MIP_SSIP
115#define SIP_STIP MIP_STIP
116
117#define PRV_U 0
118#define PRV_S 1
119#define PRV_H 2
120#define PRV_M 3
121
122#define SATP32_MODE 0x80000000
123#define SATP32_ASID 0x7FC00000
124#define SATP32_PPN 0x003FFFFF
125#define SATP64_MODE 0xF000000000000000
126#define SATP64_ASID 0x0FFFF00000000000
127#define SATP64_PPN 0x00000FFFFFFFFFFF
128
129#define SATP_MODE_OFF 0
130#define SATP_MODE_SV32 1
131#define SATP_MODE_SV39 8
132#define SATP_MODE_SV48 9
133#define SATP_MODE_SV57 10
134#define SATP_MODE_SV64 11
135
136#define PMP_R 0x01
137#define PMP_W 0x02
138#define PMP_X 0x04
139#define PMP_A 0x18
140#define PMP_L 0x80
141#define PMP_SHIFT 2
142
143#define PMP_TOR 0x08
144#define PMP_NA4 0x10
145#define PMP_NAPOT 0x18
146
147#define IRQ_S_SOFT 1
148#define IRQ_H_SOFT 2
149#define IRQ_M_SOFT 3
150#define IRQ_S_TIMER 5
151#define IRQ_H_TIMER 6
152#define IRQ_M_TIMER 7
153#define IRQ_S_EXT 9
154#define IRQ_H_EXT 10
155#define IRQ_M_EXT 11
156#define IRQ_COP 12
157#define IRQ_HOST 13
158
159#define DEFAULT_RSTVEC 0x00001000
160#define CLINT_BASE 0x02000000
161#define CLINT_SIZE 0x000c0000
162#define EXT_IO_BASE 0x40000000
163#define DRAM_BASE 0x80000000
164
165/* page table entry (PTE) fields */
166#define PTE_V 0x001 /* Valid */
167#define PTE_R 0x002 /* Read */
168#define PTE_W 0x004 /* Write */
169#define PTE_X 0x008 /* Execute */
170#define PTE_U 0x010 /* User */
171#define PTE_G 0x020 /* Global */
172#define PTE_A 0x040 /* Accessed */
173#define PTE_D 0x080 /* Dirty */
174#define PTE_SOFT 0x300 /* Reserved for Software */
175
176#define PTE_PPN_SHIFT 10
177
178#define PTE_TABLE(PTE) (((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) == PTE_V)
179
180#define INSERT_FIELD(val, which, fieldval) \
181( \
182 ((val) & ~(which)) | ((fieldval) * ((which) & ~((which)-1))) \
183) \
184
185#define csr_read(csr) \
186({ \
187 register unsigned long __rv; \
188 __asm__ volatile ("csrr %0, " STRINGIFY(csr) \
189 : "=r" (__rv)); \
190 __rv; \
191})
192
193#define csr_write(csr, val) \
194({ \
195 unsigned long __wv = (unsigned long)(val); \
196 __asm__ volatile ("csrw " STRINGIFY(csr) ", %0" \
197 : : "rK" (__wv) \
198 : "memory"); \
199})
200
201
202#define csr_read_set(csr, val) \
203({ \
204 unsigned long __rsv = (unsigned long)(val); \
205 __asm__ volatile ("csrrs %0, " STRINGIFY(csr) ", %1" \
206 : "=r" (__rsv) : "rK" (__rsv) \
207 : "memory"); \
208 __rsv; \
209})
210
211#define csr_set(csr, val) \
212({ \
213 unsigned long __sv = (unsigned long)(val); \
214 __asm__ volatile ("csrs " STRINGIFY(csr) ", %0" \
215 : : "rK" (__sv) \
216 : "memory"); \
217})
218
219#define csr_read_clear(csr, val) \
220({ \
221 unsigned long __rcv = (unsigned long)(val); \
222 __asm__ volatile ("csrrc %0, " STRINGIFY(csr) ", %1" \
223 : "=r" (__rcv) : "rK" (__rcv) \
224 : "memory"); \
225 __rcv; \
226})
227
228#define csr_clear(csr, val) \
229({ \
230 unsigned long __cv = (unsigned long)(val); \
231 __asm__ volatile ("csrc " STRINGIFY(csr) ", %0" \
232 : : "rK" (__cv) \
233 : "memory"); \
234})
235
236#endif /* CSR_H_ */