csr.h File Reference

Go to the source code of this file.

Macros
#define	MSTATUS_UIE   0x00000001
#define	MSTATUS_SIE   0x00000002
#define	MSTATUS_HIE   0x00000004
#define	MSTATUS_MIE   0x00000008
#define	MSTATUS_UPIE   0x00000010
#define	MSTATUS_SPIE   0x00000020
#define	MSTATUS_HPIE   0x00000040
#define	MSTATUS_MPIE   0x00000080
#define	MSTATUS_SPP   0x00000100
#define	MSTATUS_HPP   0x00000600
#define	MSTATUS_MPP   0x00001800
#define	MSTATUS_FS   0x00006000
#define	MSTATUS_XS   0x00018000
#define	MSTATUS_MPRV   0x00020000
#define	MSTATUS_SUM   0x00040000
#define	MSTATUS_MXR   0x00080000
#define	MSTATUS_TVM   0x00100000
#define	MSTATUS_TW   0x00200000
#define	MSTATUS_TSR   0x00400000
#define	MSTATUS32_SD   0x80000000
#define	MSTATUS_UXL   0x0000000300000000
#define	MSTATUS_SXL   0x0000000C00000000
#define	MSTATUS64_SD   0x8000000000000000
#define	SSTATUS_UIE   0x00000001
#define	SSTATUS_SIE   0x00000002
#define	SSTATUS_UPIE   0x00000010
#define	SSTATUS_SPIE   0x00000020
#define	SSTATUS_SPP   0x00000100
#define	SSTATUS_FS   0x00006000
#define	SSTATUS_XS   0x00018000
#define	SSTATUS_SUM   0x00040000
#define	SSTATUS_MXR   0x00080000
#define	SSTATUS32_SD   0x80000000
#define	SSTATUS_UXL   0x0000000300000000
#define	SSTATUS64_SD   0x8000000000000000
#define	DCSR_XDEBUGVER   (3U<<30)
#define	DCSR_NDRESET   (1<<29)
#define	DCSR_FULLRESET   (1<<28)
#define	DCSR_EBREAKM   (1<<15)
#define	DCSR_EBREAKH   (1<<14)
#define	DCSR_EBREAKS   (1<<13)
#define	DCSR_EBREAKU   (1<<12)
#define	DCSR_STOPCYCLE   (1<<10)
#define	DCSR_STOPTIME   (1<<9)
#define	DCSR_CAUSE   (7<<6)
#define	DCSR_DEBUGINT   (1<<5)
#define	DCSR_HALT   (1<<3)
#define	DCSR_STEP   (1<<2)
#define	DCSR_PRV   (3<<0)
#define	DCSR_CAUSE_NONE   0
#define	DCSR_CAUSE_SWBP   1
#define	DCSR_CAUSE_HWBP   2
#define	DCSR_CAUSE_DEBUGINT   3
#define	DCSR_CAUSE_STEP   4
#define	DCSR_CAUSE_HALT   5
#define	MCONTROL_TYPE(xlen)
#define	MCONTROL_DMODE(xlen)
#define	MCONTROL_MASKMAX(xlen)
#define	MCONTROL_SELECT   (1<<19)
#define	MCONTROL_TIMING   (1<<18)
#define	MCONTROL_ACTION   (0x3f<<12)
#define	MCONTROL_CHAIN   (1<<11)
#define	MCONTROL_MATCH   (0xf<<7)
#define	MCONTROL_M   (1<<6)
#define	MCONTROL_H   (1<<5)
#define	MCONTROL_S   (1<<4)
#define	MCONTROL_U   (1<<3)
#define	MCONTROL_EXECUTE   (1<<2)
#define	MCONTROL_STORE   (1<<1)
#define	MCONTROL_LOAD   (1<<0)
#define	MCONTROL_TYPE_NONE   0
#define	MCONTROL_TYPE_MATCH   2
#define	MCONTROL_ACTION_DEBUG_EXCEPTION   0
#define	MCONTROL_ACTION_DEBUG_MODE   1
#define	MCONTROL_ACTION_TRACE_START   2
#define	MCONTROL_ACTION_TRACE_STOP   3
#define	MCONTROL_ACTION_TRACE_EMIT   4
#define	MCONTROL_MATCH_EQUAL   0
#define	MCONTROL_MATCH_NAPOT   1
#define	MCONTROL_MATCH_GE   2
#define	MCONTROL_MATCH_LT   3
#define	MCONTROL_MATCH_MASK_LOW   4
#define	MCONTROL_MATCH_MASK_HIGH   5
#define	MIP_SSIP   (1 << IRQ_S_SOFT)
#define	MIP_HSIP   (1 << IRQ_H_SOFT)
#define	MIP_MSIP   (1 << IRQ_M_SOFT)
#define	MIP_STIP   (1 << IRQ_S_TIMER)
#define	MIP_HTIP   (1 << IRQ_H_TIMER)
#define	MIP_MTIP   (1 << IRQ_M_TIMER)
#define	MIP_SEIP   (1 << IRQ_S_EXT)
#define	MIP_HEIP   (1 << IRQ_H_EXT)
#define	MIP_MEIP   (1 << IRQ_M_EXT)
#define	SIP_SSIP   MIP_SSIP
#define	SIP_STIP   MIP_STIP
#define	COUNTEREN_CY   (1 << 0) /* cycle counter */
#define	COUNTEREN_TM   (1 << 1) /* time counter */
#define	COUNTEREN_IR   (1 << 2) /* instret counter */
#define	PRV_U   0
#define	PRV_S   1
#define	PRV_H   2
#define	PRV_M   3
#define	SATP32_MODE   0x80000000
#define	SATP32_ASID   0x7FC00000
#define	SATP32_PPN   0x003FFFFF
#define	SATP64_MODE   0xF000000000000000
#define	SATP64_ASID   0x0FFFF00000000000
#define	SATP64_PPN   0x00000FFFFFFFFFFF
#define	SATP_MODE_OFF   0
#define	SATP_MODE_SV32   1
#define	SATP_MODE_SV39   8
#define	SATP_MODE_SV48   9
#define	SATP_MODE_SV57   10
#define	SATP_MODE_SV64   11
#define	CSR_PMPCFG_BASE   0x3a0
	PMPCFG CSR base address.
#define	CSR_PMPADDR_BASE   0x3b0
	PMPADDR CSR base address.
#define	PMP_R   0x01
#define	PMP_W   0x02
#define	PMP_X   0x04
#define	PMP_A   0x18
#define	PMP_L   0x80
#define	PMP_SHIFT   2
#define	PMP_TOR   0x08
#define	PMP_NA4   0x10
#define	PMP_NAPOT   0x18
#define	IRQ_S_SOFT   1
#define	IRQ_H_SOFT   2
#define	IRQ_M_SOFT   3
#define	IRQ_S_TIMER   5
#define	IRQ_H_TIMER   6
#define	IRQ_M_TIMER   7
#define	IRQ_S_EXT   9
#define	IRQ_H_EXT   10
#define	IRQ_M_EXT   11
#define	IRQ_COP   12
#define	IRQ_HOST   13
#define	DEFAULT_RSTVEC   0x00001000
#define	CLINT_BASE   0x02000000
#define	CLINT_SIZE   0x000c0000
#define	EXT_IO_BASE   0x40000000
#define	DRAM_BASE   0x80000000
#define	PTE_V   0x001 /* Valid */
#define	PTE_R   0x002 /* Read */
#define	PTE_W   0x004 /* Write */
#define	PTE_X   0x008 /* Execute */
#define	PTE_U   0x010 /* User */
#define	PTE_G   0x020 /* Global */
#define	PTE_A   0x040 /* Accessed */
#define	PTE_D   0x080 /* Dirty */
#define	PTE_SOFT   0x300 /* Reserved for Software */
#define	PTE_PPN_SHIFT   10
#define	PTE_TABLE(PTE)
#define	INSERT_FIELD(val, which, fieldval)
#define	csr_read(csr)
#define	csr_read_imm(csr)
	Same as csr_read, but instead of a name string, the CSR is given as immediate address.
#define	csr_write(csr, val)
#define	csr_write_imm(csr, val)
	Same as csr_write, but instead of a name string, the CSR is given as immediate address.
#define	csr_read_set(csr, val)
#define	csr_set(csr, val)
#define	csr_read_clear(csr, val)
#define	csr_clear(csr, val)
#define	csr_swap(csr, val)

Macro Definition Documentation

CLINT_BASE

#define CLINT_BASE   0x02000000

CLINT_SIZE

#define CLINT_SIZE   0x000c0000

COUNTEREN_CY

#define COUNTEREN_CY   (1 << 0) /* cycle counter */

COUNTEREN_IR

#define COUNTEREN_IR   (1 << 2) /* instret counter */

COUNTEREN_TM

#define COUNTEREN_TM   (1 << 1) /* time counter */

csr_clear

#define csr_clear	(		csr,
			val )

Value:

do {                                                    \
        unsigned long __cv = (unsigned long)(val);      \
        __asm__ volatile ("csrc " STRINGIFY(csr) ", %0" \
                          :                             \
                          : "rK" (__cv)         \
                          : "memory");          \
} while (0)

CSR_PMPADDR_BASE

#define CSR_PMPADDR_BASE   0x3b0

PMPADDR CSR base address.

CSR_PMPCFG_BASE

#define CSR_PMPCFG_BASE   0x3a0

PMPCFG CSR base address.

csr_read

#define csr_read

(

csr

)

Value:

({                                                              \
        unsigned long __rv;                                     \
        __asm__ volatile ("csrr %0, " STRINGIFY(csr)            \
                                : "=r" (__rv));                 \
        __rv;                                                   \
})

csr_read_clear

#define csr_read_clear	(		csr,
			val )

Value:

({                                                              \
        unsigned long __rcv = (unsigned long)(val);             \
        __asm__ volatile ("csrrc %0, " STRINGIFY(csr) ", %1"    \
                                : "=r" (__rcv) : "rK" (__rcv)   \
                                : "memory");                    \
        __rcv;                                                  \
})

csr_read_imm

#define csr_read_imm

(

csr

)

Value:

({                                                                                         \
        register unsigned long __rv;                                                       \
        __asm__ volatile("csrr %0, %1" : "=r"(__rv) : "i"(csr));                           \
        __rv;                                                                              \
})

Same as csr_read, but instead of a name string, the CSR is given as immediate address.

csr_read_set

#define csr_read_set	(		csr,
			val )

Value:

({                                                              \
        unsigned long __rsv = (unsigned long)(val);             \
        __asm__ volatile ("csrrs %0, " STRINGIFY(csr) ", %1"    \
                                : "=r" (__rsv) : "rK" (__rsv)   \
                                : "memory");                    \
        __rsv;                                                  \
})

csr_set

#define csr_set	(		csr,
			val )

Value:

do {                                                    \
        unsigned long __sv = (unsigned long)(val);      \
        __asm__ volatile ("csrs " STRINGIFY(csr) ", %0" \
                          :                             \
                          : "rK" (__sv)         \
                          : "memory");          \
} while (0)

csr_swap

#define csr_swap	(		csr,
			val )

Value:

({                                                              \
        unsigned long __swv = (unsigned long)(val);             \
        __asm__ volatile ("csrrw %0, " STRINGIFY(csr) ", %1"    \
                          : "=r" (__swv) : "rK" (__swv)         \
                          : "memory");                          \
        __swv;                                                  \
})

csr_write

#define csr_write	(		csr,
			val )

Value:

do {                                                    \
        unsigned long __wv = (unsigned long)(val);      \
        __asm__ volatile ("csrw " STRINGIFY(csr) ", %0" \
                          :                             \
                          : "rK" (__wv)         \
                          : "memory");          \
} while (0)

csr_write_imm

#define csr_write_imm	(		csr,
			val )

Value:

do {                                                                                       \
        unsigned long __wv = (unsigned long)(val);                                         \
        __asm__ volatile("csrw %0, %1" : : "i"(csr), "rK"(__wv) : "memory");               \
} while (0)

Same as csr_write, but instead of a name string, the CSR is given as immediate address.

DCSR_CAUSE

#define DCSR_CAUSE   (7<<6)

DCSR_CAUSE_DEBUGINT

#define DCSR_CAUSE_DEBUGINT   3

DCSR_CAUSE_HALT

#define DCSR_CAUSE_HALT   5

DCSR_CAUSE_HWBP

#define DCSR_CAUSE_HWBP   2

DCSR_CAUSE_NONE

#define DCSR_CAUSE_NONE   0

DCSR_CAUSE_STEP

#define DCSR_CAUSE_STEP   4

DCSR_CAUSE_SWBP

#define DCSR_CAUSE_SWBP   1

DCSR_DEBUGINT

#define DCSR_DEBUGINT   (1<<5)

DCSR_EBREAKH

#define DCSR_EBREAKH   (1<<14)

DCSR_EBREAKM

#define DCSR_EBREAKM   (1<<15)

DCSR_EBREAKS

#define DCSR_EBREAKS   (1<<13)

DCSR_EBREAKU

#define DCSR_EBREAKU   (1<<12)

DCSR_FULLRESET

#define DCSR_FULLRESET   (1<<28)

DCSR_HALT

#define DCSR_HALT   (1<<3)

DCSR_NDRESET

#define DCSR_NDRESET   (1<<29)

DCSR_PRV

#define DCSR_PRV   (3<<0)

DCSR_STEP

#define DCSR_STEP   (1<<2)

DCSR_STOPCYCLE

#define DCSR_STOPCYCLE   (1<<10)

DCSR_STOPTIME

#define DCSR_STOPTIME   (1<<9)

DCSR_XDEBUGVER

#define DCSR_XDEBUGVER   (3U<<30)

DEFAULT_RSTVEC

#define DEFAULT_RSTVEC   0x00001000

DRAM_BASE

#define DRAM_BASE   0x80000000

EXT_IO_BASE

#define EXT_IO_BASE   0x40000000

INSERT_FIELD

#define INSERT_FIELD	(		val,
			which,
			fieldval )

Value:

(                                                                       \
        ((val) & ~(which)) | ((fieldval) * ((which) & ~((which)-1)))    \
)                                                                       \

IRQ_COP

#define IRQ_COP   12

IRQ_H_EXT

#define IRQ_H_EXT   10

IRQ_H_SOFT

#define IRQ_H_SOFT   2

IRQ_H_TIMER

#define IRQ_H_TIMER   6

IRQ_HOST

#define IRQ_HOST   13

IRQ_M_EXT

#define IRQ_M_EXT   11

IRQ_M_SOFT

#define IRQ_M_SOFT   3

IRQ_M_TIMER

#define IRQ_M_TIMER   7

IRQ_S_EXT

#define IRQ_S_EXT   9

IRQ_S_SOFT

#define IRQ_S_SOFT   1

IRQ_S_TIMER

#define IRQ_S_TIMER   5

MCONTROL_ACTION

#define MCONTROL_ACTION   (0x3f<<12)

MCONTROL_ACTION_DEBUG_EXCEPTION

#define MCONTROL_ACTION_DEBUG_EXCEPTION   0

MCONTROL_ACTION_DEBUG_MODE

#define MCONTROL_ACTION_DEBUG_MODE   1

MCONTROL_ACTION_TRACE_EMIT

#define MCONTROL_ACTION_TRACE_EMIT   4

MCONTROL_ACTION_TRACE_START

#define MCONTROL_ACTION_TRACE_START   2

MCONTROL_ACTION_TRACE_STOP

#define MCONTROL_ACTION_TRACE_STOP   3

MCONTROL_CHAIN

#define MCONTROL_CHAIN   (1<<11)

MCONTROL_DMODE

#define MCONTROL_DMODE

(

xlen

)

Value:

(1ULL<<((xlen)-5))

MCONTROL_EXECUTE

#define MCONTROL_EXECUTE   (1<<2)

MCONTROL_H

#define MCONTROL_H   (1<<5)

MCONTROL_LOAD

#define MCONTROL_LOAD   (1<<0)

MCONTROL_M

#define MCONTROL_M   (1<<6)

MCONTROL_MASKMAX

#define MCONTROL_MASKMAX

(

xlen

)

Value:

(0x3fULL<<((xlen)-11))

MCONTROL_MATCH

#define MCONTROL_MATCH   (0xf<<7)

MCONTROL_MATCH_EQUAL

#define MCONTROL_MATCH_EQUAL   0

MCONTROL_MATCH_GE

#define MCONTROL_MATCH_GE   2

MCONTROL_MATCH_LT

#define MCONTROL_MATCH_LT   3

MCONTROL_MATCH_MASK_HIGH

#define MCONTROL_MATCH_MASK_HIGH   5

MCONTROL_MATCH_MASK_LOW

#define MCONTROL_MATCH_MASK_LOW   4

MCONTROL_MATCH_NAPOT

#define MCONTROL_MATCH_NAPOT   1

MCONTROL_S

#define MCONTROL_S   (1<<4)

MCONTROL_SELECT

#define MCONTROL_SELECT   (1<<19)

MCONTROL_STORE

#define MCONTROL_STORE   (1<<1)

MCONTROL_TIMING

#define MCONTROL_TIMING   (1<<18)

MCONTROL_TYPE

#define MCONTROL_TYPE

(

xlen

)

Value:

(0xfULL<<((xlen)-4))

MCONTROL_TYPE_MATCH

#define MCONTROL_TYPE_MATCH   2

MCONTROL_TYPE_NONE

#define MCONTROL_TYPE_NONE   0

MCONTROL_U

#define MCONTROL_U   (1<<3)

MIP_HEIP

#define MIP_HEIP   (1 << IRQ_H_EXT)

MIP_HSIP

#define MIP_HSIP   (1 << IRQ_H_SOFT)

MIP_HTIP

#define MIP_HTIP   (1 << IRQ_H_TIMER)

MIP_MEIP

#define MIP_MEIP   (1 << IRQ_M_EXT)

MIP_MSIP

#define MIP_MSIP   (1 << IRQ_M_SOFT)

MIP_MTIP

#define MIP_MTIP   (1 << IRQ_M_TIMER)

MIP_SEIP

#define MIP_SEIP   (1 << IRQ_S_EXT)

MIP_SSIP

#define MIP_SSIP   (1 << IRQ_S_SOFT)

MIP_STIP

#define MIP_STIP   (1 << IRQ_S_TIMER)

MSTATUS32_SD

#define MSTATUS32_SD   0x80000000

MSTATUS64_SD

#define MSTATUS64_SD   0x8000000000000000

MSTATUS_FS

#define MSTATUS_FS   0x00006000

MSTATUS_HIE

#define MSTATUS_HIE   0x00000004

MSTATUS_HPIE

#define MSTATUS_HPIE   0x00000040

MSTATUS_HPP

#define MSTATUS_HPP   0x00000600

MSTATUS_MIE

#define MSTATUS_MIE   0x00000008

MSTATUS_MPIE

#define MSTATUS_MPIE   0x00000080

MSTATUS_MPP

#define MSTATUS_MPP   0x00001800

MSTATUS_MPRV

#define MSTATUS_MPRV   0x00020000

MSTATUS_MXR

#define MSTATUS_MXR   0x00080000

MSTATUS_SIE

#define MSTATUS_SIE   0x00000002

MSTATUS_SPIE

#define MSTATUS_SPIE   0x00000020

MSTATUS_SPP

#define MSTATUS_SPP   0x00000100

MSTATUS_SUM

#define MSTATUS_SUM   0x00040000

MSTATUS_SXL

#define MSTATUS_SXL   0x0000000C00000000

MSTATUS_TSR

#define MSTATUS_TSR   0x00400000

MSTATUS_TVM

#define MSTATUS_TVM   0x00100000

MSTATUS_TW

#define MSTATUS_TW   0x00200000

MSTATUS_UIE

#define MSTATUS_UIE   0x00000001

MSTATUS_UPIE

#define MSTATUS_UPIE   0x00000010

MSTATUS_UXL

#define MSTATUS_UXL   0x0000000300000000

MSTATUS_XS

#define MSTATUS_XS   0x00018000

PMP_A

#define PMP_A   0x18

PMP_L

#define PMP_L   0x80

PMP_NA4

#define PMP_NA4   0x10

PMP_NAPOT

#define PMP_NAPOT   0x18

PMP_R

#define PMP_R   0x01

PMP_SHIFT

#define PMP_SHIFT   2

PMP_TOR

#define PMP_TOR   0x08

PMP_W

#define PMP_W   0x02

PMP_X

#define PMP_X   0x04

PRV_H

#define PRV_H   2

PRV_M

#define PRV_M   3

PRV_S

#define PRV_S   1

PRV_U

#define PRV_U   0

PTE_A

#define PTE_A   0x040 /* Accessed */

PTE_D

#define PTE_D   0x080 /* Dirty */

PTE_G

#define PTE_G   0x020 /* Global */

PTE_PPN_SHIFT

#define PTE_PPN_SHIFT   10

PTE_R

#define PTE_R   0x002 /* Read */

PTE_SOFT

#define PTE_SOFT   0x300 /* Reserved for Software */

PTE_TABLE

#define PTE_TABLE

(

PTE

)

Value:

(((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) == PTE_V)

PTE_U

#define PTE_U   0x010 /* User */

PTE_V

#define PTE_V   0x001 /* Valid */

PTE_W

#define PTE_W   0x004 /* Write */

PTE_X

#define PTE_X   0x008 /* Execute */

SATP32_ASID

#define SATP32_ASID   0x7FC00000

SATP32_MODE

#define SATP32_MODE   0x80000000

SATP32_PPN

#define SATP32_PPN   0x003FFFFF

SATP64_ASID

#define SATP64_ASID   0x0FFFF00000000000

SATP64_MODE

#define SATP64_MODE   0xF000000000000000

SATP64_PPN

#define SATP64_PPN   0x00000FFFFFFFFFFF

SATP_MODE_OFF

#define SATP_MODE_OFF   0

SATP_MODE_SV32

#define SATP_MODE_SV32   1

SATP_MODE_SV39

#define SATP_MODE_SV39   8

SATP_MODE_SV48

#define SATP_MODE_SV48   9

SATP_MODE_SV57

#define SATP_MODE_SV57   10

SATP_MODE_SV64

#define SATP_MODE_SV64   11

SIP_SSIP

#define SIP_SSIP   MIP_SSIP

SIP_STIP

#define SIP_STIP   MIP_STIP

SSTATUS32_SD

#define SSTATUS32_SD   0x80000000

SSTATUS64_SD

#define SSTATUS64_SD   0x8000000000000000

SSTATUS_FS

#define SSTATUS_FS   0x00006000

SSTATUS_MXR

#define SSTATUS_MXR   0x00080000

SSTATUS_SIE

#define SSTATUS_SIE   0x00000002

SSTATUS_SPIE

#define SSTATUS_SPIE   0x00000020

SSTATUS_SPP

#define SSTATUS_SPP   0x00000100

SSTATUS_SUM

#define SSTATUS_SUM   0x00040000

SSTATUS_UIE

#define SSTATUS_UIE   0x00000001

SSTATUS_UPIE

#define SSTATUS_UPIE   0x00000010

SSTATUS_UXL

#define SSTATUS_UXL   0x0000000300000000

SSTATUS_XS

#define SSTATUS_XS   0x00018000