Zephyr Project API 4.4.99
A Scalable Open Source RTOS
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em32f967-pinctrl.h
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1/*
2 * SPDX-FileCopyrightText: 2024 ELAN Microelectronics Corp.
3 * SPDX-License-Identifier: Apache-2.0
4 */
5
6#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_EM32F967_PINCTRL_H_
7#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_EM32F967_PINCTRL_H_
8
9/*
10 * EM32F967 Pin Control Definitions (EM32-style)
11 */
12
13/* Pin multiplexing values for EM32F967 - based on CSV specification */
20#define EM32F967_GPIO 0 /* 000: GPIO function */
21#define EM32F967_AF1 1 /* 001: Alternate function 1 (SPI1, etc.) */
22#define EM32F967_AF2 2 /* 010: Alternate function 2 (UART, etc.) */
23#define EM32F967_AF3 3 /* 011: Alternate function 3 (Timer, 7816, etc.) */
24#define EM32F967_AF4 4 /* 100: Alternate function 4 (I2C, etc.) */
25#define EM32F967_AF5 5 /* 101: Alternate function 5 (I2C, WKUP, etc.) */
26#define EM32F967_AF6 6 /* 110: Alternate function 6 (SSP2, etc.) */
27#define EM32F967_AF7 7 /* 111: Alternate function 7 (PWM, etc.) */
28
39#define EM32F967_MUX_SHIFT 0U
40#define EM32F967_MUX_MASK 0x7U
41#define EM32F967_PIN_SHIFT 3U
42#define EM32F967_PIN_MASK 0xFU
43#define EM32F967_PORT_SHIFT 7U
44#define EM32F967_PORT_MASK 0x1U
45
53#define EM32F967_PINMUX(port, pin, mux) \
54 (((((port) - 'A') & EM32F967_PORT_MASK) << EM32F967_PORT_SHIFT) | \
55 (((pin) & EM32F967_PIN_MASK) << EM32F967_PIN_SHIFT) | \
56 (((EM32F967_##mux) & EM32F967_MUX_MASK) << EM32F967_MUX_SHIFT))
57
58/* Helper macros to extract fields from encoded pinmux value */
59#define EM32F967_DT_PINMUX_PORT(pinmux) (((pinmux) >> EM32F967_PORT_SHIFT) & EM32F967_PORT_MASK)
60
61#define EM32F967_DT_PINMUX_PIN(pinmux) (((pinmux) >> EM32F967_PIN_SHIFT) & EM32F967_PIN_MASK)
62
63#define EM32F967_DT_PINMUX_MUX(pinmux) (((pinmux) >> EM32F967_MUX_SHIFT) & EM32F967_MUX_MASK)
64
65/* Pull-up/Pull-down definitions for 5V tolerant pins (PA0-PA6) */
66#define EM32F967_PULL_NONE_5V 0 /* 00: Floating */
67#define EM32F967_PULL_UP0_5V 1 /* 01: PU0 (66KΩ@5V, 101KΩ@3.3V, 238KΩ@1.8V) */
68#define EM32F967_PULL_UP1_5V 2 /* 10: PU1 (4.7KΩ@5V, 6.41KΩ@3.3V, 12.7KΩ@1.8V) */
69#define EM32F967_PULL_DOWN_5V 3 /* 11: PD (15KΩ@5V, 21.8KΩ@3.3V, 49.6KΩ@1.8V) */
70
71/* Pull-up/Pull-down definitions for 3V pins (PA11-PA15, PB0-PB15) */
72#define EM32F967_PULL_NONE_3V 0 /* 00: Floating */
73#define EM32F967_PULL_UP0_3V 1 /* 01: PU0 (66KΩ@3.3V, 140KΩ@1.8V) */
74#define EM32F967_PULL_UP1_3V 2 /* 10: PU1 (4.7KΩ@3.3V, 8.53KΩ@1.8V) */
75#define EM32F967_PULL_DOWN_3V 3 /* 11: PD (15KΩ@3.3V, 25.2KΩ@1.8V) */
76
77/* Drive strength definitions */
78#define EM32F967_DRIVE_NORMAL 0 /* Normal drive strength */
79#define EM32F967_DRIVE_HIGH 1 /* High drive strength (Load=30pF) */
80
101#define EM32F967_IO_NONE 0U
102
103/* Explicit op builders (shift = bit position, width = field width in bits) */
115#define EM32F967_IO1(shift, width, val) \
116 ((1U << 8) | (((shift) & 0x1FU) << 9) | ((((width) - 1U) & 0x3U) << 14) | \
117 (((val) & 0xFU) << 16))
118
131#define EM32F967_IO2(shift, width, val) \
132 ((1U << 20) | (((shift) & 0x1FU) << 21) | ((((width) - 1U) & 0x3U) << 26) | \
133 (((val) & 0xFU) << 28))
134
135/* Convenience helpers for slot 1 (combine with EM32F967_IO2() via bitwise OR) */
143#define EM32F967_IO_SET_BIT(pos) EM32F967_IO1((pos), 1U, 1U)
151#define EM32F967_IO_CLR_BIT(pos) EM32F967_IO1((pos), 1U, 0U)
160#define EM32F967_IO_SET_2BIT(pos, val) EM32F967_IO1((pos), 2U, (val))
168#define EM32F967_IO_CLR_2BIT(pos) EM32F967_IO1((pos), 2U, 0U)
169
179#define EM32F967_PINMUX_IO(port, pin, mux, ioshare) (EM32F967_PINMUX(port, pin, mux) | (ioshare))
180
181#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_EM32F967_PINCTRL_H_ */