em32f967-pinctrl.h File Reference

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Macros
#define	EM32F967_GPIO   0 /* 000: GPIO function */
	GPIO mux function selector (mux field value 0).
#define	EM32F967_AF1   1 /* 001: Alternate function 1 (SPI1, etc.) */
#define	EM32F967_AF2   2 /* 010: Alternate function 2 (UART, etc.) */
#define	EM32F967_AF3   3 /* 011: Alternate function 3 (Timer, 7816, etc.) */
#define	EM32F967_AF4   4 /* 100: Alternate function 4 (I2C, etc.) */
#define	EM32F967_AF5   5 /* 101: Alternate function 5 (I2C, WKUP, etc.) */
#define	EM32F967_AF6   6 /* 110: Alternate function 6 (SSP2, etc.) */
#define	EM32F967_AF7   7 /* 111: Alternate function 7 (PWM, etc.) */
#define	EM32F967_MUX_SHIFT   0U
	Pin configuration bit field encoding (EM32-style).
#define	EM32F967_MUX_MASK   0x7U
#define	EM32F967_PIN_SHIFT   3U
#define	EM32F967_PIN_MASK   0xFU
#define	EM32F967_PORT_SHIFT   7U
#define	EM32F967_PORT_MASK   0x1U
#define	EM32F967_PINMUX(port, pin, mux)
	EM32F967 Pin Multiplexing Macro (EM32-style).
#define	EM32F967_DT_PINMUX_PORT(pinmux)
#define	EM32F967_DT_PINMUX_PIN(pinmux)
#define	EM32F967_DT_PINMUX_MUX(pinmux)
#define	EM32F967_PULL_NONE_5V   0 /* 00: Floating */
#define	EM32F967_PULL_UP0_5V   1 /* 01: PU0 (66KΩ@5V, 101KΩ@3.3V, 238KΩ@1.8V) */
#define	EM32F967_PULL_UP1_5V   2 /* 10: PU1 (4.7KΩ@5V, 6.41KΩ@3.3V, 12.7KΩ@1.8V) */
#define	EM32F967_PULL_DOWN_5V   3 /* 11: PD (15KΩ@5V, 21.8KΩ@3.3V, 49.6KΩ@1.8V) */
#define	EM32F967_PULL_NONE_3V   0 /* 00: Floating */
#define	EM32F967_PULL_UP0_3V   1 /* 01: PU0 (66KΩ@3.3V, 140KΩ@1.8V) */
#define	EM32F967_PULL_UP1_3V   2 /* 10: PU1 (4.7KΩ@3.3V, 8.53KΩ@1.8V) */
#define	EM32F967_PULL_DOWN_3V   3 /* 11: PD (15KΩ@3.3V, 25.2KΩ@1.8V) */
#define	EM32F967_DRIVE_NORMAL   0 /* Normal drive strength */
#define	EM32F967_DRIVE_HIGH   1 /* High drive strength (Load=30pF) */
#define	EM32F967_IO_NONE   0U
	Embedded IP_SHARE operations carried inside the pinmux cell.
#define	EM32F967_IO1(shift, width, val)
	Build the first (slot 1) embedded IP_SHARE operation.
#define	EM32F967_IO2(shift, width, val)
	Build the second (slot 2) embedded IP_SHARE operation.
#define	EM32F967_IO_SET_BIT(pos)
	Slot 1 helper: set a single IP_SHARE bit.
#define	EM32F967_IO_CLR_BIT(pos)
	Slot 1 helper: clear a single IP_SHARE bit.
#define	EM32F967_IO_SET_2BIT(pos, val)
	Slot 1 helper: write a 2-bit IP_SHARE field.
#define	EM32F967_IO_CLR_2BIT(pos)
	Slot 1 helper: clear a 2-bit IP_SHARE field.
#define	EM32F967_PINMUX_IO(port, pin, mux, ioshare)
	EM32F967 pinmux macro with embedded IP_SHARE operation(s).

Macro Definition Documentation

EM32F967_AF1

#define EM32F967_AF1   1 /* 001: Alternate function 1 (SPI1, etc.) */

EM32F967_AF2

#define EM32F967_AF2   2 /* 010: Alternate function 2 (UART, etc.) */

EM32F967_AF3

#define EM32F967_AF3   3 /* 011: Alternate function 3 (Timer, 7816, etc.) */

EM32F967_AF4

#define EM32F967_AF4   4 /* 100: Alternate function 4 (I2C, etc.) */

EM32F967_AF5

#define EM32F967_AF5   5 /* 101: Alternate function 5 (I2C, WKUP, etc.) */

EM32F967_AF6

#define EM32F967_AF6   6 /* 110: Alternate function 6 (SSP2, etc.) */

EM32F967_AF7

#define EM32F967_AF7   7 /* 111: Alternate function 7 (PWM, etc.) */

EM32F967_DRIVE_HIGH

#define EM32F967_DRIVE_HIGH   1 /* High drive strength (Load=30pF) */

EM32F967_DRIVE_NORMAL

#define EM32F967_DRIVE_NORMAL   0 /* Normal drive strength */

EM32F967_DT_PINMUX_MUX

#define EM32F967_DT_PINMUX_MUX

(

pinmux

)

Value:

(((pinmux) >> EM32F967_MUX_SHIFT) & EM32F967_MUX_MASK)

EM32F967_DT_PINMUX_PIN

#define EM32F967_DT_PINMUX_PIN

(

pinmux

)

Value:

(((pinmux) >> EM32F967_PIN_SHIFT) & EM32F967_PIN_MASK)

EM32F967_DT_PINMUX_PORT

#define EM32F967_DT_PINMUX_PORT

(

pinmux

)

Value:

(((pinmux) >> EM32F967_PORT_SHIFT) & EM32F967_PORT_MASK)

EM32F967_GPIO

#define EM32F967_GPIO   0 /* 000: GPIO function */

GPIO mux function selector (mux field value 0).

Selects the plain GPIO function (no alternate function) for a pin when used as the mux argument of EM32F967_PINMUX / EM32F967_PINMUX_IO.

EM32F967_IO1

#define EM32F967_IO1	(		shift,
			width,
			val )

Value:

((1U << 8) | (((shift) & 0x1FU) << 9) | ((((width) - 1U) & 0x3U) << 14) |                  \
 (((val) & 0xFU) << 16))

Build the first (slot 1) embedded IP_SHARE operation.

Encodes a single IP_SHARE read-modify-write operation into pinmux bits [19:8] (valid flag, shift, width-1 and value). Combine with EM32F967_IO2 via bitwise OR to encode a second operation.

Parameters

shift	Bit position (0-31) of the field within the IP_SHARE register.
width	Field width in bits (1-4).
val	Value to write into the field.

EM32F967_IO2

#define EM32F967_IO2	(		shift,
			width,
			val )

Value:

((1U << 20) | (((shift) & 0x1FU) << 21) | ((((width) - 1U) & 0x3U) << 26) |                \
 (((val) & 0xFU) << 28))

Build the second (slot 2) embedded IP_SHARE operation.

Encodes a single IP_SHARE read-modify-write operation into pinmux bits [31:20] (valid flag, shift, width-1 and value). Combine with EM32F967_IO1 (or its convenience helpers) via bitwise OR to encode a second operation in the same pinmux cell.

Parameters

shift	Bit position (0-31) of the field within the IP_SHARE register.
width	Field width in bits (1-4).
val	Value to write into the field.

EM32F967_IO_CLR_2BIT

#define EM32F967_IO_CLR_2BIT

(

pos

)

Value:

EM32F967_IO1((pos), 2U, 0U)

Slot 1 helper: clear a 2-bit IP_SHARE field.

Equivalent to EM32F967_IO1 with a 2-bit field whose value is 0.

Parameters

pos	Bit position (0-31) of the 2-bit field in the IP_SHARE register.

EM32F967_IO_CLR_BIT

#define EM32F967_IO_CLR_BIT

(

pos

)

Value:

EM32F967_IO1((pos), 1U, 0U)

Slot 1 helper: clear a single IP_SHARE bit.

Equivalent to EM32F967_IO1 with a 1-bit field whose value is 0.

Parameters

pos	Bit position (0-31) to clear in the IP_SHARE register.

EM32F967_IO_NONE

#define EM32F967_IO_NONE   0U

Embedded IP_SHARE operations carried inside the pinmux cell.

The high 24 bits of the pinmux value (bits [31:8]) may encode up to two IP_SHARE read-modify-write operations. The pinctrl driver (drivers/pinctrl/pinctrl_em32.c, em32_apply_ioshare_from_pinmux()) decodes and applies them when present, instead of falling back to the built-in em32_ioshare_table[] lookup.

Bit layout (must stay in sync with the PINMUX_IO* defines in the driver):

bit [ 8] io1_valid (1 = first IP_SHARE op present) bits [13:9] io1_shift (bit position 0-31 in IP_SHARE) bits [15:14] io1_width_m1 (field width minus 1: 0 = 1 bit) bits [19:16] io1_value (value written at io1_shift) bit [20] io2_valid (1 = second IP_SHARE op present) bits [25:21] io2_shift bits [27:26] io2_width_m1 bits [31:28] io2_value

EM32F967_IO_SET_2BIT

#define EM32F967_IO_SET_2BIT	(		pos,
			val )

Value:

EM32F967_IO1((pos), 2U, (val))

Slot 1 helper: write a 2-bit IP_SHARE field.

Equivalent to EM32F967_IO1 with a 2-bit field.

Parameters

pos	Bit position (0-31) of the 2-bit field in the IP_SHARE register.
val	Value (0-3) to write into the field.

EM32F967_IO_SET_BIT

#define EM32F967_IO_SET_BIT

(

pos

)

Value:

EM32F967_IO1((pos), 1U, 1U)

Slot 1 helper: set a single IP_SHARE bit.

Equivalent to EM32F967_IO1 with a 1-bit field whose value is 1.

Parameters

pos	Bit position (0-31) to set in the IP_SHARE register.

EM32F967_MUX_MASK

#define EM32F967_MUX_MASK   0x7U

EM32F967_MUX_SHIFT

#define EM32F967_MUX_SHIFT   0U

Pin configuration bit field encoding (EM32-style).

Fields:

• mux [ 0 : 2 ] - Multiplexing function (3 bits)
• pin [ 3 : 6 ] - Pin number (4 bits, 0-15)
• port [ 7 : 7 ] - Port identifier (1 bit, 0=PA, 1=PB)

This encoding allows up to 2 ports, 16 pins per port, and 8 mux functions

EM32F967_PIN_MASK

#define EM32F967_PIN_MASK   0xFU

EM32F967_PIN_SHIFT

#define EM32F967_PIN_SHIFT   3U

EM32F967_PINMUX

#define EM32F967_PINMUX	(		port,
			pin,
			mux )

Value:

(((((port) - 'A') & EM32F967_PORT_MASK) << EM32F967_PORT_SHIFT) |                          \
 (((pin) & EM32F967_PIN_MASK) << EM32F967_PIN_SHIFT) |                                     \
 (((EM32F967_##mux) & EM32F967_MUX_MASK) << EM32F967_MUX_SHIFT))

EM32F967 Pin Multiplexing Macro (EM32-style).

Parameters

port	Port identifier ('A' or 'B')
pin	Pin number (0-15)
mux	Multiplexing function (GPIO, AF1-AF7)

EM32F967_PINMUX_IO

#define EM32F967_PINMUX_IO	(		port,
			pin,
			mux,
			ioshare )

Value:

(EM32F967_PINMUX(port, pin, mux) | (ioshare))

EM32F967 pinmux macro with embedded IP_SHARE operation(s).

Parameters

port	Port identifier ('A' or 'B')
pin	Pin number (0-15)
mux	Multiplexing function (GPIO, AF1-AF7)
ioshare	One or two IP_SHARE ops built with EM32F967_IO_* / EM32F967_IO1 / EM32F967_IO2, or EM32F967_IO_NONE.

EM32F967_PORT_MASK

#define EM32F967_PORT_MASK   0x1U

EM32F967_PORT_SHIFT

#define EM32F967_PORT_SHIFT   7U

EM32F967_PULL_DOWN_3V

#define EM32F967_PULL_DOWN_3V   3 /* 11: PD (15KΩ@3.3V, 25.2KΩ@1.8V) */

EM32F967_PULL_DOWN_5V

#define EM32F967_PULL_DOWN_5V   3 /* 11: PD (15KΩ@5V, 21.8KΩ@3.3V, 49.6KΩ@1.8V) */

EM32F967_PULL_NONE_3V

#define EM32F967_PULL_NONE_3V   0 /* 00: Floating */

EM32F967_PULL_NONE_5V

#define EM32F967_PULL_NONE_5V   0 /* 00: Floating */

EM32F967_PULL_UP0_3V

#define EM32F967_PULL_UP0_3V   1 /* 01: PU0 (66KΩ@3.3V, 140KΩ@1.8V) */

EM32F967_PULL_UP0_5V

#define EM32F967_PULL_UP0_5V   1 /* 01: PU0 (66KΩ@5V, 101KΩ@3.3V, 238KΩ@1.8V) */

EM32F967_PULL_UP1_3V

#define EM32F967_PULL_UP1_3V   2 /* 10: PU1 (4.7KΩ@3.3V, 8.53KΩ@1.8V) */

EM32F967_PULL_UP1_5V

#define EM32F967_PULL_UP1_5V   2 /* 10: PU1 (4.7KΩ@5V, 6.41KΩ@3.3V, 12.7KΩ@1.8V) */