gd32c2x1.h

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/*
 * Copyright (c) 2026 GigaDevice Semiconductor Inc.
 *
 * SPDX-License-Identifier: Apache-2.0
 */

 
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_GD32C2X1_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_GD32C2X1_H_
 
#include "gd32-common.h"

 
#define GD32_AHB1RST_OFFSET 0x10U 
#define GD32_AHB2RST_OFFSET 0x14U 
#define GD32_APBRST_OFFSET  0x24U 


 
/* AHB1 peripherals */
#define GD32_RESET_CRC GD32_RESET_CONFIG(AHB1RST, 12U) 
#define GD32_RESET_DMA GD32_RESET_CONFIG(AHB1RST, 21U) 
 
/* AHB2 peripherals */
#define GD32_RESET_GPIOA GD32_RESET_CONFIG(AHB2RST, 17U) 
#define GD32_RESET_GPIOB GD32_RESET_CONFIG(AHB2RST, 18U) 
#define GD32_RESET_GPIOC GD32_RESET_CONFIG(AHB2RST, 19U) 
#define GD32_RESET_GPIOD GD32_RESET_CONFIG(AHB2RST, 20U) 
#define GD32_RESET_GPIOF GD32_RESET_CONFIG(AHB2RST, 22U) 
 
/* APB peripherals */
#define GD32_RESET_SYSCFG  GD32_RESET_CONFIG(APBRST, 0U)  
#define GD32_RESET_CMP     GD32_RESET_CONFIG(APBRST, 1U)  
#define GD32_RESET_WWDGT   GD32_RESET_CONFIG(APBRST, 8U)  
#define GD32_RESET_ADC     GD32_RESET_CONFIG(APBRST, 9U)  
#define GD32_RESET_TIMER0  GD32_RESET_CONFIG(APBRST, 10U) 
#define GD32_RESET_TIMER2  GD32_RESET_CONFIG(APBRST, 11U) 
#define GD32_RESET_SPI0    GD32_RESET_CONFIG(APBRST, 12U) 
#define GD32_RESET_SPI1    GD32_RESET_CONFIG(APBRST, 13U) 
#define GD32_RESET_USART0  GD32_RESET_CONFIG(APBRST, 14U) 
#define GD32_RESET_USART1  GD32_RESET_CONFIG(APBRST, 15U) 
#define GD32_RESET_TIMER13 GD32_RESET_CONFIG(APBRST, 16U) 
#define GD32_RESET_TIMER15 GD32_RESET_CONFIG(APBRST, 17U) 
#define GD32_RESET_TIMER16 GD32_RESET_CONFIG(APBRST, 18U) 
#define GD32_RESET_USART2  GD32_RESET_CONFIG(APBRST, 19U) 
#define GD32_RESET_I2C0    GD32_RESET_CONFIG(APBRST, 21U) 
#define GD32_RESET_I2C1    GD32_RESET_CONFIG(APBRST, 22U) 
#define GD32_RESET_PMU     GD32_RESET_CONFIG(APBRST, 28U) 

 
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_RESET_GD32C2X1_H_ */