gd32c2x1.h File Reference

GD32C2X1 reset controller definitions for device tree bindings. More...

#include "gd32-common.h"

Go to the source code of this file.

Macros
Register offsets
#define	GD32_AHB1RST_OFFSET   0x10U
	AHB1 peripheral reset register offset.
#define	GD32_AHB2RST_OFFSET   0x14U
	AHB2 peripheral reset register offset.
#define	GD32_APBRST_OFFSET   0x24U
	APB peripheral reset register offset.
Reset definitions for peripherals
#define	GD32_RESET_CRC   GD32_RESET_CONFIG(AHB1RST, 12U)
	CRC reset.
#define	GD32_RESET_DMA   GD32_RESET_CONFIG(AHB1RST, 21U)
	DMA reset.
#define	GD32_RESET_GPIOA   GD32_RESET_CONFIG(AHB2RST, 17U)
	GPIOA reset.
#define	GD32_RESET_GPIOB   GD32_RESET_CONFIG(AHB2RST, 18U)
	GPIOB reset.
#define	GD32_RESET_GPIOC   GD32_RESET_CONFIG(AHB2RST, 19U)
	GPIOC reset.
#define	GD32_RESET_GPIOD   GD32_RESET_CONFIG(AHB2RST, 20U)
	GPIOD reset.
#define	GD32_RESET_GPIOF   GD32_RESET_CONFIG(AHB2RST, 22U)
	GPIOF reset.
#define	GD32_RESET_SYSCFG   GD32_RESET_CONFIG(APBRST, 0U)
	SYSCFG reset.
#define	GD32_RESET_CMP   GD32_RESET_CONFIG(APBRST, 1U)
	Comparator reset.
#define	GD32_RESET_WWDGT   GD32_RESET_CONFIG(APBRST, 8U)
	Window watchdog reset.
#define	GD32_RESET_ADC   GD32_RESET_CONFIG(APBRST, 9U)
	ADC reset.
#define	GD32_RESET_TIMER0   GD32_RESET_CONFIG(APBRST, 10U)
	TIMER0 reset.
#define	GD32_RESET_TIMER2   GD32_RESET_CONFIG(APBRST, 11U)
	TIMER2 reset.
#define	GD32_RESET_SPI0   GD32_RESET_CONFIG(APBRST, 12U)
	SPI0 reset.
#define	GD32_RESET_SPI1   GD32_RESET_CONFIG(APBRST, 13U)
	SPI1 reset.
#define	GD32_RESET_USART0   GD32_RESET_CONFIG(APBRST, 14U)
	USART0 reset.
#define	GD32_RESET_USART1   GD32_RESET_CONFIG(APBRST, 15U)
	USART1 reset.
#define	GD32_RESET_TIMER13   GD32_RESET_CONFIG(APBRST, 16U)
	TIMER13 reset.
#define	GD32_RESET_TIMER15   GD32_RESET_CONFIG(APBRST, 17U)
	TIMER15 reset.
#define	GD32_RESET_TIMER16   GD32_RESET_CONFIG(APBRST, 18U)
	TIMER16 reset.
#define	GD32_RESET_USART2   GD32_RESET_CONFIG(APBRST, 19U)
	USART2 reset.
#define	GD32_RESET_I2C0   GD32_RESET_CONFIG(APBRST, 21U)
	I2C0 reset.
#define	GD32_RESET_I2C1   GD32_RESET_CONFIG(APBRST, 22U)
	I2C1 reset.
#define	GD32_RESET_PMU   GD32_RESET_CONFIG(APBRST, 28U)
	PMU reset.

Detailed Description

GD32C2X1 reset controller definitions for device tree bindings.

Macro Definition Documentation

GD32_AHB1RST_OFFSET

#define GD32_AHB1RST_OFFSET   0x10U

AHB1 peripheral reset register offset.

GD32_AHB2RST_OFFSET

#define GD32_AHB2RST_OFFSET   0x14U

AHB2 peripheral reset register offset.

GD32_APBRST_OFFSET

#define GD32_APBRST_OFFSET   0x24U

APB peripheral reset register offset.

GD32_RESET_ADC

#define GD32_RESET_ADC   GD32_RESET_CONFIG(APBRST, 9U)

ADC reset.

GD32_RESET_CMP

#define GD32_RESET_CMP   GD32_RESET_CONFIG(APBRST, 1U)

Comparator reset.

GD32_RESET_CRC

#define GD32_RESET_CRC   GD32_RESET_CONFIG(AHB1RST, 12U)

CRC reset.

GD32_RESET_DMA

#define GD32_RESET_DMA   GD32_RESET_CONFIG(AHB1RST, 21U)

DMA reset.

GD32_RESET_GPIOA

#define GD32_RESET_GPIOA   GD32_RESET_CONFIG(AHB2RST, 17U)

GPIOA reset.

GD32_RESET_GPIOB

#define GD32_RESET_GPIOB   GD32_RESET_CONFIG(AHB2RST, 18U)

GPIOB reset.

GD32_RESET_GPIOC

#define GD32_RESET_GPIOC   GD32_RESET_CONFIG(AHB2RST, 19U)

GPIOC reset.

GD32_RESET_GPIOD

#define GD32_RESET_GPIOD   GD32_RESET_CONFIG(AHB2RST, 20U)

GPIOD reset.

GD32_RESET_GPIOF

#define GD32_RESET_GPIOF   GD32_RESET_CONFIG(AHB2RST, 22U)

GPIOF reset.

GD32_RESET_I2C0

#define GD32_RESET_I2C0   GD32_RESET_CONFIG(APBRST, 21U)

I2C0 reset.

GD32_RESET_I2C1

#define GD32_RESET_I2C1   GD32_RESET_CONFIG(APBRST, 22U)

I2C1 reset.

GD32_RESET_PMU

#define GD32_RESET_PMU   GD32_RESET_CONFIG(APBRST, 28U)

PMU reset.

GD32_RESET_SPI0

#define GD32_RESET_SPI0   GD32_RESET_CONFIG(APBRST, 12U)

SPI0 reset.

GD32_RESET_SPI1

#define GD32_RESET_SPI1   GD32_RESET_CONFIG(APBRST, 13U)

SPI1 reset.

GD32_RESET_SYSCFG

#define GD32_RESET_SYSCFG   GD32_RESET_CONFIG(APBRST, 0U)

SYSCFG reset.

GD32_RESET_TIMER0

#define GD32_RESET_TIMER0   GD32_RESET_CONFIG(APBRST, 10U)

TIMER0 reset.

GD32_RESET_TIMER13

#define GD32_RESET_TIMER13   GD32_RESET_CONFIG(APBRST, 16U)

TIMER13 reset.

GD32_RESET_TIMER15

#define GD32_RESET_TIMER15   GD32_RESET_CONFIG(APBRST, 17U)

TIMER15 reset.

GD32_RESET_TIMER16

#define GD32_RESET_TIMER16   GD32_RESET_CONFIG(APBRST, 18U)

TIMER16 reset.

GD32_RESET_TIMER2

#define GD32_RESET_TIMER2   GD32_RESET_CONFIG(APBRST, 11U)

TIMER2 reset.

GD32_RESET_USART0

#define GD32_RESET_USART0   GD32_RESET_CONFIG(APBRST, 14U)

USART0 reset.

GD32_RESET_USART1

#define GD32_RESET_USART1   GD32_RESET_CONFIG(APBRST, 15U)

USART1 reset.

GD32_RESET_USART2

#define GD32_RESET_USART2   GD32_RESET_CONFIG(APBRST, 19U)

USART2 reset.

GD32_RESET_WWDGT

#define GD32_RESET_WWDGT   GD32_RESET_CONFIG(APBRST, 8U)

Window watchdog reset.