Zephyr Project API 3.7.0
A Scalable Open Source RTOS
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ifx_cat1-pinctrl.h
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1/* Copyright 2022 Cypress Semiconductor Corporation (an Infineon company) or
2 * an affiliate of Cypress Semiconductor Corporation
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
14#define SOC_PINMUX_PORT_POS (0)
15#define SOC_PINMUX_PORT_MASK (0xFFul << SOC_PINMUX_PORT_POS)
16#define SOC_PINMUX_PIN_POS (8)
17#define SOC_PINMUX_PIN_MASK (0xFFul << SOC_PINMUX_PIN_POS)
18#define SOC_PINMUX_HSIOM_FUNC_POS (16)
19#define SOC_PINMUX_HSIOM_MASK (0xFFul << SOC_PINMUX_HSIOM_FUNC_POS)
20#define SOC_PINMUX_SIGNAL_POS (24)
21#define SOC_PINMUX_SIGNAL_MASK (0xFFul << SOC_PINMUX_SIGNAL_POS)
22
26#define HSIOM_SEL_GPIO (0)
27#define HSIOM_SEL_GPIO_DSI (1)
28#define HSIOM_SEL_DSI_DSI (2)
29#define HSIOM_SEL_DSI_GPIO (3)
30#define HSIOM_SEL_AMUXA (4)
31#define HSIOM_SEL_AMUXB (5)
32#define HSIOM_SEL_AMUXA_DSI (6)
33#define HSIOM_SEL_AMUXB_DSI (7)
34#define HSIOM_SEL_ACT_0 (8)
35#define HSIOM_SEL_ACT_1 (9)
36#define HSIOM_SEL_ACT_2 (10)
37#define HSIOM_SEL_ACT_3 (11)
38#define HSIOM_SEL_DS_0 (12)
39#define HSIOM_SEL_DS_1 (13)
40#define HSIOM_SEL_DS_2 (14)
41#define HSIOM_SEL_DS_3 (15)
42#define HSIOM_SEL_ACT_4 (16)
43#define HSIOM_SEL_ACT_5 (17)
44#define HSIOM_SEL_ACT_6 (18)
45#define HSIOM_SEL_ACT_7 (19)
46#define HSIOM_SEL_ACT_8 (20)
47#define HSIOM_SEL_ACT_9 (21)
48#define HSIOM_SEL_ACT_10 (22)
49#define HSIOM_SEL_ACT_11 (23)
50#define HSIOM_SEL_ACT_12 (24)
51#define HSIOM_SEL_ACT_13 (25)
52#define HSIOM_SEL_ACT_14 (26)
53#define HSIOM_SEL_ACT_15 (27)
54#define HSIOM_SEL_DS_4 (28)
55#define HSIOM_SEL_DS_5 (29)
56#define HSIOM_SEL_DS_6 (30)
57#define HSIOM_SEL_DS_7 (31)
58
62#define DT_CAT1_DRIVE_MODE_INFO(peripheral_signal) \
63 CAT1_PIN_MAP_DRIVE_MODE_##peripheral_signal
64
68#define DT_CAT1_PINMUX(port, pin, hsiom) \
69 ((port << SOC_PINMUX_PORT_POS) | \
70 (pin << SOC_PINMUX_PIN_POS) | \
71 (hsiom << SOC_PINMUX_HSIOM_FUNC_POS))
72
73/* Redefine DT GPIO label (Px) to CYHAL port macros (CYHAL_PORT_x) */
74#define P0 CYHAL_PORT_0
75#define P1 CYHAL_PORT_1
76#define P2 CYHAL_PORT_2
77#define P3 CYHAL_PORT_3
78#define P4 CYHAL_PORT_4
79#define P5 CYHAL_PORT_5
80#define P6 CYHAL_PORT_6
81#define P7 CYHAL_PORT_7
82#define P8 CYHAL_PORT_8
83#define P9 CYHAL_PORT_9
84#define P10 CYHAL_PORT_10
85#define P11 CYHAL_PORT_11
86#define P12 CYHAL_PORT_12
87#define P13 CYHAL_PORT_13
88#define P14 CYHAL_PORT_14
89#define P15 CYHAL_PORT_15
90#define P16 CYHAL_PORT_16
91#define P17 CYHAL_PORT_17
92#define P18 CYHAL_PORT_18
93#define P19 CYHAL_PORT_19
94#define P20 CYHAL_PORT_20
95
96/* Returns CYHAL GPIO from Board device tree GPIO configuration
97 * CYHAL_GET_GPIO(port_number, pin_number),
98 * port_number = ((REG ADDR of node) - (REG ADDR of gpio_prt0)) / (REG SIZE of gpio_prt0)
99 * pin_number = DT_PHA_BY_IDX(node, gpios_prop, 0, pin)
100 */
101#define DT_GET_CYHAL_GPIO_FROM_DT_GPIOS(node, gpios_prop) \
102 CYHAL_GET_GPIO( \
103 (DT_REG_ADDR_BY_IDX(DT_GPIO_CTLR_BY_IDX(node, gpios_prop, 0), 0) - \
104 DT_REG_ADDR_BY_IDX(DT_NODELABEL(gpio_prt0), 0)) / \
105 DT_REG_ADDR_BY_IDX(DT_NODELABEL(gpio_prt0), 1), \
106 DT_PHA_BY_IDX(node, gpios_prop, 0, pin) \
107 )