Zephyr Project API 3.7.0
A Scalable Open Source RTOS
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ifx_cat1-pinctrl.h File Reference

Go to the source code of this file.

Macros

#define SOC_PINMUX_PORT_POS   (0)
 Pin control binding helper.
 
#define SOC_PINMUX_PORT_MASK   (0xFFul << SOC_PINMUX_PORT_POS)
 
#define SOC_PINMUX_PIN_POS   (8)
 
#define SOC_PINMUX_PIN_MASK   (0xFFul << SOC_PINMUX_PIN_POS)
 
#define SOC_PINMUX_HSIOM_FUNC_POS   (16)
 
#define SOC_PINMUX_HSIOM_MASK   (0xFFul << SOC_PINMUX_HSIOM_FUNC_POS)
 
#define SOC_PINMUX_SIGNAL_POS   (24)
 
#define SOC_PINMUX_SIGNAL_MASK   (0xFFul << SOC_PINMUX_SIGNAL_POS)
 
#define HSIOM_SEL_GPIO   (0)
 Functions are defined using HSIOM SEL.
 
#define HSIOM_SEL_GPIO_DSI   (1)
 
#define HSIOM_SEL_DSI_DSI   (2)
 
#define HSIOM_SEL_DSI_GPIO   (3)
 
#define HSIOM_SEL_AMUXA   (4)
 
#define HSIOM_SEL_AMUXB   (5)
 
#define HSIOM_SEL_AMUXA_DSI   (6)
 
#define HSIOM_SEL_AMUXB_DSI   (7)
 
#define HSIOM_SEL_ACT_0   (8)
 
#define HSIOM_SEL_ACT_1   (9)
 
#define HSIOM_SEL_ACT_2   (10)
 
#define HSIOM_SEL_ACT_3   (11)
 
#define HSIOM_SEL_DS_0   (12)
 
#define HSIOM_SEL_DS_1   (13)
 
#define HSIOM_SEL_DS_2   (14)
 
#define HSIOM_SEL_DS_3   (15)
 
#define HSIOM_SEL_ACT_4   (16)
 
#define HSIOM_SEL_ACT_5   (17)
 
#define HSIOM_SEL_ACT_6   (18)
 
#define HSIOM_SEL_ACT_7   (19)
 
#define HSIOM_SEL_ACT_8   (20)
 
#define HSIOM_SEL_ACT_9   (21)
 
#define HSIOM_SEL_ACT_10   (22)
 
#define HSIOM_SEL_ACT_11   (23)
 
#define HSIOM_SEL_ACT_12   (24)
 
#define HSIOM_SEL_ACT_13   (25)
 
#define HSIOM_SEL_ACT_14   (26)
 
#define HSIOM_SEL_ACT_15   (27)
 
#define HSIOM_SEL_DS_4   (28)
 
#define HSIOM_SEL_DS_5   (29)
 
#define HSIOM_SEL_DS_6   (30)
 
#define HSIOM_SEL_DS_7   (31)
 
#define DT_CAT1_DRIVE_MODE_INFO(peripheral_signal)    CAT1_PIN_MAP_DRIVE_MODE_##peripheral_signal
 Macro to set drive mode.
 
#define DT_CAT1_PINMUX(port, pin, hsiom)
 Macro to set pin control information (from pinctrl node)
 
#define P0   CYHAL_PORT_0
 
#define P1   CYHAL_PORT_1
 
#define P2   CYHAL_PORT_2
 
#define P3   CYHAL_PORT_3
 
#define P4   CYHAL_PORT_4
 
#define P5   CYHAL_PORT_5
 
#define P6   CYHAL_PORT_6
 
#define P7   CYHAL_PORT_7
 
#define P8   CYHAL_PORT_8
 
#define P9   CYHAL_PORT_9
 
#define P10   CYHAL_PORT_10
 
#define P11   CYHAL_PORT_11
 
#define P12   CYHAL_PORT_12
 
#define P13   CYHAL_PORT_13
 
#define P14   CYHAL_PORT_14
 
#define P15   CYHAL_PORT_15
 
#define P16   CYHAL_PORT_16
 
#define P17   CYHAL_PORT_17
 
#define P18   CYHAL_PORT_18
 
#define P19   CYHAL_PORT_19
 
#define P20   CYHAL_PORT_20
 
#define DT_GET_CYHAL_GPIO_FROM_DT_GPIOS(node, gpios_prop)
 

Macro Definition Documentation

◆ DT_CAT1_DRIVE_MODE_INFO

#define DT_CAT1_DRIVE_MODE_INFO (   peripheral_signal)     CAT1_PIN_MAP_DRIVE_MODE_##peripheral_signal

Macro to set drive mode.

◆ DT_CAT1_PINMUX

#define DT_CAT1_PINMUX (   port,
  pin,
  hsiom 
)
Value:
((port << SOC_PINMUX_PORT_POS) | \
(pin << SOC_PINMUX_PIN_POS) | \
#define SOC_PINMUX_HSIOM_FUNC_POS
Definition ifx_cat1-pinctrl.h:18
#define SOC_PINMUX_PIN_POS
Definition ifx_cat1-pinctrl.h:16
#define SOC_PINMUX_PORT_POS
Pin control binding helper.
Definition ifx_cat1-pinctrl.h:14

Macro to set pin control information (from pinctrl node)

◆ DT_GET_CYHAL_GPIO_FROM_DT_GPIOS

#define DT_GET_CYHAL_GPIO_FROM_DT_GPIOS (   node,
  gpios_prop 
)
Value:
CYHAL_GET_GPIO( \
(DT_REG_ADDR_BY_IDX(DT_GPIO_CTLR_BY_IDX(node, gpios_prop, 0), 0) - \
DT_REG_ADDR_BY_IDX(DT_NODELABEL(gpio_prt0), 0)) / \
DT_REG_ADDR_BY_IDX(DT_NODELABEL(gpio_prt0), 1), \
DT_PHA_BY_IDX(node, gpios_prop, 0, pin) \
)
#define DT_NODELABEL(label)
Get a node identifier for a node label.
Definition devicetree.h:200
#define DT_PHA_BY_IDX(node_id, pha, idx, cell)
Get a phandle-array specifier cell value at an index.
Definition devicetree.h:1407
#define DT_GPIO_CTLR_BY_IDX(node_id, gpio_pha, idx)
Get the node identifier for the controller phandle from a gpio phandle-array property at an index.
Definition gpio.h:53
#define DT_REG_ADDR_BY_IDX(node_id, idx)
Get the base address of the register block at index idx.
Definition devicetree.h:2252

◆ HSIOM_SEL_ACT_0

#define HSIOM_SEL_ACT_0   (8)

◆ HSIOM_SEL_ACT_1

#define HSIOM_SEL_ACT_1   (9)

◆ HSIOM_SEL_ACT_10

#define HSIOM_SEL_ACT_10   (22)

◆ HSIOM_SEL_ACT_11

#define HSIOM_SEL_ACT_11   (23)

◆ HSIOM_SEL_ACT_12

#define HSIOM_SEL_ACT_12   (24)

◆ HSIOM_SEL_ACT_13

#define HSIOM_SEL_ACT_13   (25)

◆ HSIOM_SEL_ACT_14

#define HSIOM_SEL_ACT_14   (26)

◆ HSIOM_SEL_ACT_15

#define HSIOM_SEL_ACT_15   (27)

◆ HSIOM_SEL_ACT_2

#define HSIOM_SEL_ACT_2   (10)

◆ HSIOM_SEL_ACT_3

#define HSIOM_SEL_ACT_3   (11)

◆ HSIOM_SEL_ACT_4

#define HSIOM_SEL_ACT_4   (16)

◆ HSIOM_SEL_ACT_5

#define HSIOM_SEL_ACT_5   (17)

◆ HSIOM_SEL_ACT_6

#define HSIOM_SEL_ACT_6   (18)

◆ HSIOM_SEL_ACT_7

#define HSIOM_SEL_ACT_7   (19)

◆ HSIOM_SEL_ACT_8

#define HSIOM_SEL_ACT_8   (20)

◆ HSIOM_SEL_ACT_9

#define HSIOM_SEL_ACT_9   (21)

◆ HSIOM_SEL_AMUXA

#define HSIOM_SEL_AMUXA   (4)

◆ HSIOM_SEL_AMUXA_DSI

#define HSIOM_SEL_AMUXA_DSI   (6)

◆ HSIOM_SEL_AMUXB

#define HSIOM_SEL_AMUXB   (5)

◆ HSIOM_SEL_AMUXB_DSI

#define HSIOM_SEL_AMUXB_DSI   (7)

◆ HSIOM_SEL_DS_0

#define HSIOM_SEL_DS_0   (12)

◆ HSIOM_SEL_DS_1

#define HSIOM_SEL_DS_1   (13)

◆ HSIOM_SEL_DS_2

#define HSIOM_SEL_DS_2   (14)

◆ HSIOM_SEL_DS_3

#define HSIOM_SEL_DS_3   (15)

◆ HSIOM_SEL_DS_4

#define HSIOM_SEL_DS_4   (28)

◆ HSIOM_SEL_DS_5

#define HSIOM_SEL_DS_5   (29)

◆ HSIOM_SEL_DS_6

#define HSIOM_SEL_DS_6   (30)

◆ HSIOM_SEL_DS_7

#define HSIOM_SEL_DS_7   (31)

◆ HSIOM_SEL_DSI_DSI

#define HSIOM_SEL_DSI_DSI   (2)

◆ HSIOM_SEL_DSI_GPIO

#define HSIOM_SEL_DSI_GPIO   (3)

◆ HSIOM_SEL_GPIO

#define HSIOM_SEL_GPIO   (0)

Functions are defined using HSIOM SEL.

◆ HSIOM_SEL_GPIO_DSI

#define HSIOM_SEL_GPIO_DSI   (1)

◆ P0

#define P0   CYHAL_PORT_0

◆ P1

#define P1   CYHAL_PORT_1

◆ P10

#define P10   CYHAL_PORT_10

◆ P11

#define P11   CYHAL_PORT_11

◆ P12

#define P12   CYHAL_PORT_12

◆ P13

#define P13   CYHAL_PORT_13

◆ P14

#define P14   CYHAL_PORT_14

◆ P15

#define P15   CYHAL_PORT_15

◆ P16

#define P16   CYHAL_PORT_16

◆ P17

#define P17   CYHAL_PORT_17

◆ P18

#define P18   CYHAL_PORT_18

◆ P19

#define P19   CYHAL_PORT_19

◆ P2

#define P2   CYHAL_PORT_2

◆ P20

#define P20   CYHAL_PORT_20

◆ P3

#define P3   CYHAL_PORT_3

◆ P4

#define P4   CYHAL_PORT_4

◆ P5

#define P5   CYHAL_PORT_5

◆ P6

#define P6   CYHAL_PORT_6

◆ P7

#define P7   CYHAL_PORT_7

◆ P8

#define P8   CYHAL_PORT_8

◆ P9

#define P9   CYHAL_PORT_9

◆ SOC_PINMUX_HSIOM_FUNC_POS

#define SOC_PINMUX_HSIOM_FUNC_POS   (16)

◆ SOC_PINMUX_HSIOM_MASK

#define SOC_PINMUX_HSIOM_MASK   (0xFFul << SOC_PINMUX_HSIOM_FUNC_POS)

◆ SOC_PINMUX_PIN_MASK

#define SOC_PINMUX_PIN_MASK   (0xFFul << SOC_PINMUX_PIN_POS)

◆ SOC_PINMUX_PIN_POS

#define SOC_PINMUX_PIN_POS   (8)

◆ SOC_PINMUX_PORT_MASK

#define SOC_PINMUX_PORT_MASK   (0xFFul << SOC_PINMUX_PORT_POS)

◆ SOC_PINMUX_PORT_POS

#define SOC_PINMUX_PORT_POS   (0)

Pin control binding helper.

Bit definition in PINMUX field

◆ SOC_PINMUX_SIGNAL_MASK

#define SOC_PINMUX_SIGNAL_MASK   (0xFFul << SOC_PINMUX_SIGNAL_POS)

◆ SOC_PINMUX_SIGNAL_POS

#define SOC_PINMUX_SIGNAL_POS   (24)