kinetis_sim.h File Reference

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Macros
#define	KINETIS_SIM_CORESYS_CLK   0
#define	KINETIS_SIM_PLATFORM_CLK   1
#define	KINETIS_SIM_BUS_CLK   2
#define	KINETIS_SIM_FAST_PERIPHERAL_CLK   5
#define	KINETIS_SIM_LPO_CLK   19
#define	KINETIS_SIM_DMAMUX_CLK   KINETIS_SIM_BUS_CLK
#define	KINETIS_SIM_DMA_CLK   KINETIS_SIM_CORESYS_CLK
#define	KINETIS_SIM_SIM_SOPT7   7
#define	KINETIS_SIM_OSCERCLK   8
#define	KINETIS_SIM_MCGIRCLK   12
#define	KINETIS_SIM_MCGPCLK   18
#define	KINETIS_SIM_PLLFLLSEL_MCGFLLCLK   0
#define	KINETIS_SIM_PLLFLLSEL_MCGPLLCLK   1
#define	KINETIS_SIM_PLLFLLSEL_IRC48MHZ   3
#define	KINETIS_SIM_ER32KSEL_OSC32KCLK   0
#define	KINETIS_SIM_ER32KSEL_RTC   2
#define	KINETIS_SIM_ER32KSEL_LPO1KHZ   3
#define	KINETIS_SIM_ENET_CLK   4321
#define	KINETIS_SIM_ENET_1588_CLK   4322
#define	KINETIS_SIM_CMP_CLK   4323
#define	KINETIS_SIM_VREF_CLK   4324
#define	KINETIS_SIM_CLOCK(name, offset, bits)
	Build a 3-cell SIM clock specifier.
#define	KINETIS_SIM_CLOCK_MUX(name, offset, bits, mux_shift, mux_val)
	Build a 3-cell SIM clock specifier with mux configuration.

Macro Definition Documentation

KINETIS_SIM_BUS_CLK

#define KINETIS_SIM_BUS_CLK   2

KINETIS_SIM_CLOCK

#define KINETIS_SIM_CLOCK	(		name,
			offset,
			bits )

Value:

        KINETIS_SIM_CLOCK_ID(name, offset, bits) offset bits

Build a 3-cell SIM clock specifier.

Expands to <id offset bits> where id encodes gate and rate information, and offset/bits are kept explicit for readability and for consumers (e.g. ADC16) that read them as separate cells.

Parameters

name	Clock name selector (KINETIS_SIM_*_CLK)
offset	Gate register offset (e.g. 0x1034)
bits	Gate bit index (0..31)

KINETIS_SIM_CLOCK_MUX

#define KINETIS_SIM_CLOCK_MUX	(		name,
			offset,
			bits,
			mux_shift,
			mux_val )

Value:

        KINETIS_SIM_CLOCK_ID_MUX(name, offset, bits, mux_shift, mux_val) offset bits

Build a 3-cell SIM clock specifier with mux configuration.

Like KINETIS_SIM_CLOCK but also encodes the mux register field and value needed for clock_control_configure() support.

Parameters

name	Clock name selector (KINETIS_SIM_*_CLK)
offset	Gate register offset
bits	Gate bit index (0..31)
mux_shift	Bit shift of the mux field in the mux register (e.g. SOPT2)
mux_val	Value to write into the mux field

KINETIS_SIM_CMP_CLK

#define KINETIS_SIM_CMP_CLK   4323

KINETIS_SIM_CORESYS_CLK

#define KINETIS_SIM_CORESYS_CLK   0

KINETIS_SIM_DMA_CLK

#define KINETIS_SIM_DMA_CLK   KINETIS_SIM_CORESYS_CLK

KINETIS_SIM_DMAMUX_CLK

#define KINETIS_SIM_DMAMUX_CLK   KINETIS_SIM_BUS_CLK

KINETIS_SIM_ENET_1588_CLK

#define KINETIS_SIM_ENET_1588_CLK   4322

KINETIS_SIM_ENET_CLK

#define KINETIS_SIM_ENET_CLK   4321

KINETIS_SIM_ER32KSEL_LPO1KHZ

#define KINETIS_SIM_ER32KSEL_LPO1KHZ   3

KINETIS_SIM_ER32KSEL_OSC32KCLK

#define KINETIS_SIM_ER32KSEL_OSC32KCLK   0

KINETIS_SIM_ER32KSEL_RTC

#define KINETIS_SIM_ER32KSEL_RTC   2

KINETIS_SIM_FAST_PERIPHERAL_CLK

#define KINETIS_SIM_FAST_PERIPHERAL_CLK   5

KINETIS_SIM_LPO_CLK

#define KINETIS_SIM_LPO_CLK   19

KINETIS_SIM_MCGIRCLK

#define KINETIS_SIM_MCGIRCLK   12

KINETIS_SIM_MCGPCLK

#define KINETIS_SIM_MCGPCLK   18

KINETIS_SIM_OSCERCLK

#define KINETIS_SIM_OSCERCLK   8

KINETIS_SIM_PLATFORM_CLK

#define KINETIS_SIM_PLATFORM_CLK   1

KINETIS_SIM_PLLFLLSEL_IRC48MHZ

#define KINETIS_SIM_PLLFLLSEL_IRC48MHZ   3

KINETIS_SIM_PLLFLLSEL_MCGFLLCLK

#define KINETIS_SIM_PLLFLLSEL_MCGFLLCLK   0

KINETIS_SIM_PLLFLLSEL_MCGPLLCLK

#define KINETIS_SIM_PLLFLLSEL_MCGPLLCLK   1

KINETIS_SIM_SIM_SOPT7

#define KINETIS_SIM_SIM_SOPT7   7

KINETIS_SIM_VREF_CLK

#define KINETIS_SIM_VREF_CLK   4324