mchp-xec-dmac.h File Reference

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Macros
#define	DMA_MCHP_XEC_TRIG_SRC_I2C_SMB0_TARG   0x0
	Vendor-specific DMA peripheral triggering sources.
#define	DMA_MCHP_XEC_TRIG_SRC_I2C_SMB0_CTRL   0x1
#define	DMA_MCHP_XEC_TRIG_SRC_I2C_SMB1_TARG   0x2
#define	DMA_MCHP_XEC_TRIG_SRC_I2C_SMB1_CTRL   0x3
#define	DMA_MCHP_XEC_TRIG_SRC_I2C_SMB2_TARG   0x4
#define	DMA_MCHP_XEC_TRIG_SRC_I2C_SMB2_CTRL   0x5
#define	DMA_MCHP_XEC_TRIG_SRC_I2C_SMB3_TARG   0x6
#define	DMA_MCHP_XEC_TRIG_SRC_I2C_SMB3_CTRL   0x7
#define	DMA_MCHP_XEC_TRIG_SRC_I2C_SMB4_TARG   0x8
#define	DMA_MCHP_XEC_TRIG_SRC_I2C_SMB4_CTRL   0x9
#define	DMA_MCHP_XEC_TRIG_SRC_QMSPI0_TX   0xA
#define	DMA_MCHP_XEC_TRIG_SRC_QMSPI0_RX   0xB
#define	DMA_MCHP_XEC_TRIG_SRC_GPSPI0_TX   0xC
#define	DMA_MCHP_XEC_TRIG_SRC_GPSPI0_RX   0xD
#define	DMA_MCHP_XEC_TRIG_SRC_GPSPI1_TX   0xE
#define	DMA_MCHP_XEC_TRIG_SRC_GPSPI1_RX   0xF
#define	DMA_MCHP_XEC_TRIG_SRC_I3C_HC0_TX   0x10
#define	DMA_MCHP_XEC_TRIG_SRC_I3C_HC0_RX   0x11
#define	DMA_MCHP_XEC_TRIG_SRC_I3C_SC0_TX   0x12
#define	DMA_MCHP_XEC_TRIG_SRC_I3C_SC0_RX   0x13

Macro Definition Documentation

DMA_MCHP_XEC_TRIG_SRC_GPSPI0_RX

#define DMA_MCHP_XEC_TRIG_SRC_GPSPI0_RX   0xD

DMA_MCHP_XEC_TRIG_SRC_GPSPI0_TX

#define DMA_MCHP_XEC_TRIG_SRC_GPSPI0_TX   0xC

DMA_MCHP_XEC_TRIG_SRC_GPSPI1_RX

#define DMA_MCHP_XEC_TRIG_SRC_GPSPI1_RX   0xF

DMA_MCHP_XEC_TRIG_SRC_GPSPI1_TX

#define DMA_MCHP_XEC_TRIG_SRC_GPSPI1_TX   0xE

DMA_MCHP_XEC_TRIG_SRC_I2C_SMB0_CTRL

#define DMA_MCHP_XEC_TRIG_SRC_I2C_SMB0_CTRL   0x1

DMA_MCHP_XEC_TRIG_SRC_I2C_SMB0_TARG

#define DMA_MCHP_XEC_TRIG_SRC_I2C_SMB0_TARG   0x0

Vendor-specific DMA peripheral triggering sources.

A valid triggering source should be provided when DMA is configured for peripheral to peripheral or memory to peripheral transactions.

DMA_MCHP_XEC_TRIG_SRC_I2C_SMB1_CTRL

#define DMA_MCHP_XEC_TRIG_SRC_I2C_SMB1_CTRL   0x3

DMA_MCHP_XEC_TRIG_SRC_I2C_SMB1_TARG

#define DMA_MCHP_XEC_TRIG_SRC_I2C_SMB1_TARG   0x2

DMA_MCHP_XEC_TRIG_SRC_I2C_SMB2_CTRL

#define DMA_MCHP_XEC_TRIG_SRC_I2C_SMB2_CTRL   0x5

DMA_MCHP_XEC_TRIG_SRC_I2C_SMB2_TARG

#define DMA_MCHP_XEC_TRIG_SRC_I2C_SMB2_TARG   0x4

DMA_MCHP_XEC_TRIG_SRC_I2C_SMB3_CTRL

#define DMA_MCHP_XEC_TRIG_SRC_I2C_SMB3_CTRL   0x7

DMA_MCHP_XEC_TRIG_SRC_I2C_SMB3_TARG

#define DMA_MCHP_XEC_TRIG_SRC_I2C_SMB3_TARG   0x6

DMA_MCHP_XEC_TRIG_SRC_I2C_SMB4_CTRL

#define DMA_MCHP_XEC_TRIG_SRC_I2C_SMB4_CTRL   0x9

DMA_MCHP_XEC_TRIG_SRC_I2C_SMB4_TARG

#define DMA_MCHP_XEC_TRIG_SRC_I2C_SMB4_TARG   0x8

DMA_MCHP_XEC_TRIG_SRC_I3C_HC0_RX

#define DMA_MCHP_XEC_TRIG_SRC_I3C_HC0_RX   0x11

DMA_MCHP_XEC_TRIG_SRC_I3C_HC0_TX

#define DMA_MCHP_XEC_TRIG_SRC_I3C_HC0_TX   0x10

DMA_MCHP_XEC_TRIG_SRC_I3C_SC0_RX

#define DMA_MCHP_XEC_TRIG_SRC_I3C_SC0_RX   0x13

DMA_MCHP_XEC_TRIG_SRC_I3C_SC0_TX

#define DMA_MCHP_XEC_TRIG_SRC_I3C_SC0_TX   0x12

DMA_MCHP_XEC_TRIG_SRC_QMSPI0_RX

#define DMA_MCHP_XEC_TRIG_SRC_QMSPI0_RX   0xB

DMA_MCHP_XEC_TRIG_SRC_QMSPI0_TX

#define DMA_MCHP_XEC_TRIG_SRC_QMSPI0_TX   0xA