Clock control header file for Microchip sam_d5x_e5x family. More...

#include <zephyr/dt-bindings/clock/mchp_sam_d5x_e5x_clock.h>

Data Structures
struct	clock_mchp_subsys_xosc_config_t

struct	clock_mchp_subsys_dfll_config_t

struct	clock_mchp_subsys_fdpll_config_t

struct	clock_mchp_subsys_rtc_config_t

struct	clock_mchp_subsys_osc32k_config_t

struct	clock_mchp_subsys_gclkgen_config_t

struct	clock_mchp_subsys_gclkperiph_config_t

struct	clock_mchp_subsys_mclkcpu_config_t
	MCLK configuration structure. More...

Typedefs
typedef uint32_t *	clock_mchp_rate_t
	clock rate datatype

Enumerations
enum	clock_mchp_gclkgen_t { CLOCK_MCHP_GCLKGEN_GEN0 , CLOCK_MCHP_GCLKGEN_GEN1 , CLOCK_MCHP_GCLKGEN_GEN2 , CLOCK_MCHP_GCLKGEN_GEN3 , CLOCK_MCHP_GCLKGEN_GEN4 , CLOCK_MCHP_GCLKGEN_GEN5 , CLOCK_MCHP_GCLKGEN_GEN6 , CLOCK_MCHP_GCLKGEN_GEN7 , CLOCK_MCHP_GCLKGEN_GEN8 , CLOCK_MCHP_GCLKGEN_GEN9 , CLOCK_MCHP_GCLKGEN_GEN10 , CLOCK_MCHP_GCLKGEN_GEN11 }
	GCLK generator numbers . More...

enum	clock_mchp_fdpll_src_clock_t { CLOCK_MCHP_FDPLL_SRC_GCLK0 , CLOCK_MCHP_FDPLL_SRC_GCLK1 , CLOCK_MCHP_FDPLL_SRC_GCLK2 , CLOCK_MCHP_FDPLL_SRC_GCLK3 , CLOCK_MCHP_FDPLL_SRC_GCLK4 , CLOCK_MCHP_FDPLL_SRC_GCLK5 , CLOCK_MCHP_FDPLL_SRC_GCLK6 , CLOCK_MCHP_FDPLL_SRC_GCLK7 , CLOCK_MCHP_FDPLL_SRC_GCLK8 , CLOCK_MCHP_FDPLL_SRC_GCLK9 , CLOCK_MCHP_FDPLL_SRC_GCLK10 , CLOCK_MCHP_FDPLL_SRC_GCLK11 , CLOCK_MCHP_FDPLL_SRC_XOSC32K , CLOCK_MCHP_FDPLL_SRC_XOSC0 , CLOCK_MCHP_FDPLL_SRC_XOSC1 , CLOCK_MCHP_FDPLL_SRC_MAX = CLOCK_MCHP_FDPLL_SRC_XOSC1 }
	FDPLL source clocks . More...

enum	clock_mchp_rtc_src_clock_t { CLOCK_MCHP_RTC_SRC_ULP1K = OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K , CLOCK_MCHP_RTC_SRC_ULP32K = OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K , CLOCK_MCHP_RTC_SRC_XOSC1K = OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K , CLOCK_MCHP_RTC_SRC_XOSC32K = OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K }
	RTC source clocks . More...

enum	clock_mchp_gclk_src_clock_t { CLOCK_MCHP_GCLK_SRC_XOSC0 , CLOCK_MCHP_GCLK_SRC_XOSC1 , CLOCK_MCHP_GCLK_SRC_GCLKPIN , CLOCK_MCHP_GCLK_SRC_GCLKGEN1 , CLOCK_MCHP_GCLK_SRC_OSCULP32K , CLOCK_MCHP_GCLK_SRC_XOSC32K , CLOCK_MCHP_GCLK_SRC_DFLL , CLOCK_MCHP_GCLK_SRC_FDPLL0 , CLOCK_MCHP_GCLK_SRC_FDPLL1 , CLOCK_MCHP_GCLK_SRC_MAX = CLOCK_MCHP_GCLK_SRC_FDPLL1 }
	Gclk Generator source clocks . More...

enum	clock_mchp_mclk_cpu_div_t { CLOCK_MCHP_MCLK_CPU_DIV_1 = 1 , CLOCK_MCHP_MCLK_CPU_DIV_2 = 2 , CLOCK_MCHP_MCLK_CPU_DIV_4 = 4 , CLOCK_MCHP_MCLK_CPU_DIV_8 = 8 , CLOCK_MCHP_MCLK_CPU_DIV_16 = 16 , CLOCK_MCHP_MCLK_CPU_DIV_32 = 32 , CLOCK_MCHP_MCLK_CPU_DIV_64 = 64 , CLOCK_MCHP_MCLK_CPU_DIV_128 = 128 }
	division ratio of mclk prescaler for CPU More...

Detailed Description

Clock control header file for Microchip sam_d5x_e5x family.

This file provides clock driver interface definitions and structures for sam_d5x_e5x family

Typedef Documentation

◆ clock_mchp_rate_t

typedef uint32_t* clock_mchp_rate_t

clock rate datatype

Used for setting a clock rate

Enumeration Type Documentation

◆ clock_mchp_fdpll_src_clock_t

enum clock_mchp_fdpll_src_clock_t

FDPLL source clocks .

Enumerator
CLOCK_MCHP_FDPLL_SRC_GCLK0
CLOCK_MCHP_FDPLL_SRC_GCLK1
CLOCK_MCHP_FDPLL_SRC_GCLK2
CLOCK_MCHP_FDPLL_SRC_GCLK3
CLOCK_MCHP_FDPLL_SRC_GCLK4
CLOCK_MCHP_FDPLL_SRC_GCLK5
CLOCK_MCHP_FDPLL_SRC_GCLK6
CLOCK_MCHP_FDPLL_SRC_GCLK7
CLOCK_MCHP_FDPLL_SRC_GCLK8
CLOCK_MCHP_FDPLL_SRC_GCLK9
CLOCK_MCHP_FDPLL_SRC_GCLK10
CLOCK_MCHP_FDPLL_SRC_GCLK11
CLOCK_MCHP_FDPLL_SRC_XOSC32K
CLOCK_MCHP_FDPLL_SRC_XOSC0
CLOCK_MCHP_FDPLL_SRC_XOSC1
CLOCK_MCHP_FDPLL_SRC_MAX

◆ clock_mchp_gclk_src_clock_t

enum clock_mchp_gclk_src_clock_t

Gclk Generator source clocks .

Enumerator
CLOCK_MCHP_GCLK_SRC_XOSC0
CLOCK_MCHP_GCLK_SRC_XOSC1
CLOCK_MCHP_GCLK_SRC_GCLKPIN
CLOCK_MCHP_GCLK_SRC_GCLKGEN1
CLOCK_MCHP_GCLK_SRC_OSCULP32K
CLOCK_MCHP_GCLK_SRC_XOSC32K
CLOCK_MCHP_GCLK_SRC_DFLL
CLOCK_MCHP_GCLK_SRC_FDPLL0
CLOCK_MCHP_GCLK_SRC_FDPLL1
CLOCK_MCHP_GCLK_SRC_MAX

◆ clock_mchp_gclkgen_t

enum clock_mchp_gclkgen_t

GCLK generator numbers .

Enumerator
CLOCK_MCHP_GCLKGEN_GEN0
CLOCK_MCHP_GCLKGEN_GEN1
CLOCK_MCHP_GCLKGEN_GEN2
CLOCK_MCHP_GCLKGEN_GEN3
CLOCK_MCHP_GCLKGEN_GEN4
CLOCK_MCHP_GCLKGEN_GEN5
CLOCK_MCHP_GCLKGEN_GEN6
CLOCK_MCHP_GCLKGEN_GEN7
CLOCK_MCHP_GCLKGEN_GEN8
CLOCK_MCHP_GCLKGEN_GEN9
CLOCK_MCHP_GCLKGEN_GEN10
CLOCK_MCHP_GCLKGEN_GEN11

◆ clock_mchp_mclk_cpu_div_t

enum clock_mchp_mclk_cpu_div_t

division ratio of mclk prescaler for CPU

Enumerator
CLOCK_MCHP_MCLK_CPU_DIV_1
CLOCK_MCHP_MCLK_CPU_DIV_2
CLOCK_MCHP_MCLK_CPU_DIV_4
CLOCK_MCHP_MCLK_CPU_DIV_8
CLOCK_MCHP_MCLK_CPU_DIV_16
CLOCK_MCHP_MCLK_CPU_DIV_32
CLOCK_MCHP_MCLK_CPU_DIV_64
CLOCK_MCHP_MCLK_CPU_DIV_128

◆ clock_mchp_rtc_src_clock_t

enum clock_mchp_rtc_src_clock_t

RTC source clocks .

Enumerator
CLOCK_MCHP_RTC_SRC_ULP1K
CLOCK_MCHP_RTC_SRC_ULP32K
CLOCK_MCHP_RTC_SRC_XOSC1K
CLOCK_MCHP_RTC_SRC_XOSC32K

Data Structures

Typedefs

Enumerations