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◆ MSS_RESET_ID_ATHENA
      
        
          | #define MSS_RESET_ID_ATHENA   0x1c | 
      
 
 
◆ MSS_RESET_ID_CAN0
      
        
          | #define MSS_RESET_ID_CAN0   0xe | 
      
 
 
◆ MSS_RESET_ID_CAN1
      
        
          | #define MSS_RESET_ID_CAN1   0xf | 
      
 
 
◆ MSS_RESET_ID_CFM
      
        
          | #define MSS_RESET_ID_CFM   0x1d | 
      
 
 
◆ MSS_RESET_ID_DDRC
      
        
          | #define MSS_RESET_ID_DDRC   0x17 | 
      
 
 
◆ MSS_RESET_ID_ENVM
      
        
          | #define MSS_RESET_ID_ENVM   0x0 | 
      
 
 
◆ MSS_RESET_ID_FIC0
      
        
          | #define MSS_RESET_ID_FIC0   0x18 | 
      
 
 
◆ MSS_RESET_ID_FIC1
      
        
          | #define MSS_RESET_ID_FIC1   0x19 | 
      
 
 
◆ MSS_RESET_ID_FIC2
      
        
          | #define MSS_RESET_ID_FIC2   0x1a | 
      
 
 
◆ MSS_RESET_ID_FIC3
      
        
          | #define MSS_RESET_ID_FIC3   0x1b | 
      
 
 
◆ MSS_RESET_ID_GPIO0
      
        
          | #define MSS_RESET_ID_GPIO0   0x14 | 
      
 
 
◆ MSS_RESET_ID_GPIO1
      
        
          | #define MSS_RESET_ID_GPIO1   0x15 | 
      
 
 
◆ MSS_RESET_ID_GPIO2
      
        
          | #define MSS_RESET_ID_GPIO2   0x16 | 
      
 
 
◆ MSS_RESET_ID_I2C0
      
        
          | #define MSS_RESET_ID_I2C0   0xc | 
      
 
 
◆ MSS_RESET_ID_I2C1
      
        
          | #define MSS_RESET_ID_I2C1   0xd | 
      
 
 
◆ MSS_RESET_ID_MAC0
      
        
          | #define MSS_RESET_ID_MAC0   0x1 | 
      
 
 
◆ MSS_RESET_ID_MAC1
      
        
          | #define MSS_RESET_ID_MAC1   0x2 | 
      
 
 
◆ MSS_RESET_ID_MMC
      
        
          | #define MSS_RESET_ID_MMC   0x3 | 
      
 
 
◆ MSS_RESET_ID_MMUART0
      
        
          | #define MSS_RESET_ID_MMUART0   0x5 | 
      
 
 
◆ MSS_RESET_ID_MMUART1
      
        
          | #define MSS_RESET_ID_MMUART1   0x6 | 
      
 
 
◆ MSS_RESET_ID_MMUART2
      
        
          | #define MSS_RESET_ID_MMUART2   0x7 | 
      
 
 
◆ MSS_RESET_ID_MMUART3
      
        
          | #define MSS_RESET_ID_MMUART3   0x8 | 
      
 
 
◆ MSS_RESET_ID_MMUART4
      
        
          | #define MSS_RESET_ID_MMUART4   0x9 | 
      
 
 
◆ MSS_RESET_ID_QSPI
      
        
          | #define MSS_RESET_ID_QSPI   0x13 | 
      
 
 
◆ MSS_RESET_ID_RSVD
      
        
          | #define MSS_RESET_ID_RSVD   0x11 | 
      
 
 
◆ MSS_RESET_ID_RTC
      
        
          | #define MSS_RESET_ID_RTC   0x12 | 
      
 
 
◆ MSS_RESET_ID_SPI0
      
        
          | #define MSS_RESET_ID_SPI0   0xa | 
      
 
 
◆ MSS_RESET_ID_SPI1
      
        
          | #define MSS_RESET_ID_SPI1   0xb | 
      
 
 
◆ MSS_RESET_ID_TIMER
      
        
          | #define MSS_RESET_ID_TIMER   0x4 | 
      
 
 
◆ MSS_RESET_ID_USB
      
        
          | #define MSS_RESET_ID_USB   0x10 |