mchp_pic32cm_sg_gc_clock.h File Reference

List clock subsystem IDs for pic32cm_sg_gc family. More...

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Macros
#define	MCHP_CLOCK_DERIVE_ID(type, mclkmaskreg, mclkmaskbit, gclkperiph, inst)
	Derive a 32-bit clock subsystem identifier.
XOSC_TYPE Clock IDs
#define	CLOCK_MCHP_XOSC_ID   MCHP_CLOCK_DERIVE_ID(0, 0x3f, 0x3f, 0x3f, 0)
	External Oscillator (XOSC) clock ID.
#define	CLOCK_MCHP_XOSC_ID_MAX   (0)
	Maximum index for XOSC clock IDs.
DFLL48M_TYPE Clock IDs
#define	CLOCK_MCHP_DFLL48M_ID   MCHP_CLOCK_DERIVE_ID(1, 0x3f, 0x3f, 0, 0)
	DFLL48M (48 MHz Digital Frequency Locked Loop) clock ID.
#define	CLOCK_MCHP_DFLL48M_ID_MAX   (0)
	Maximum index for DFLL48M clock IDs.
DPLL_TYPE Clock IDs
#define	CLOCK_MCHP_DPLL_ID_DPLL0   MCHP_CLOCK_DERIVE_ID(2, 0x3f, 0x3f, 1, 0)
	DPLL0 clock ID.
#define	CLOCK_MCHP_DPLL_ID_MAX   (0)
	Maximum index for DPLL clock IDs.
DPLL_OUT_TYPE Clock IDs
#define	CLOCK_MCHP_DPLL0_ID_OUT0   MCHP_CLOCK_DERIVE_ID(3, 0x3f, 0x3f, 0x3f, 0)
	DPLL0 Output 0 clock ID.
#define	CLOCK_MCHP_DPLL0_ID_OUT1   MCHP_CLOCK_DERIVE_ID(3, 0x3f, 0x3f, 0x3f, 1)
	DPLL0 Output 1 clock ID.
#define	CLOCK_MCHP_DPLL0_ID_OUT2   MCHP_CLOCK_DERIVE_ID(3, 0x3f, 0x3f, 0x3f, 2)
	DPLL0 Output 2 clock ID.
#define	CLOCK_MCHP_DPLL0_ID_OUT3   MCHP_CLOCK_DERIVE_ID(3, 0x3f, 0x3f, 0x3f, 3)
	DPLL0 Output 3 clock ID.
#define	CLOCK_MCHP_DPLL0_ID_OUT4   MCHP_CLOCK_DERIVE_ID(3, 0x3f, 0x3f, 0x3f, 4)
	DPLL0 Output 4 clock ID.
#define	CLOCK_MCHP_DPLL_OUT_ID_MAX   (4)
	Maximum index for DPLL output clock IDs.
RTC_TYPE Clock IDs
#define	CLOCK_MCHP_RTC_ID   MCHP_CLOCK_DERIVE_ID(4, 0x3f, 0x3f, 0x3f, 0)
	Real-Time Counter (RTC) clock ID.
#define	CLOCK_MCHP_RTC_ID_MAX   (0)
	Maximum index for RTC clock IDs.
XOSC32K_TYPE Clock IDs
#define	CLOCK_MCHP_XOSC32K_ID   MCHP_CLOCK_DERIVE_ID(5, 0x3f, 0x3f, 0x3f, 0)
	32 kHz External Oscillator (XOSC32K) clock ID.
#define	CLOCK_MCHP_XOSC32K_ID_MAX   (0)
	Maximum index for XOSC32K clock IDs.
GCLKGEN_TYPE Clock IDs
#define	CLOCK_MCHP_GCLKGEN_ID_GEN0   MCHP_CLOCK_DERIVE_ID(6, 0x3f, 0x3f, 0x3f, 0)
	Generic Clock Generator 0 ID.
#define	CLOCK_MCHP_GCLKGEN_ID_GEN1   MCHP_CLOCK_DERIVE_ID(6, 0x3f, 0x3f, 0x3f, 1)
	Generic Clock Generator 1 ID.
#define	CLOCK_MCHP_GCLKGEN_ID_GEN2   MCHP_CLOCK_DERIVE_ID(6, 0x3f, 0x3f, 0x3f, 2)
	Generic Clock Generator 2 ID.
#define	CLOCK_MCHP_GCLKGEN_ID_GEN3   MCHP_CLOCK_DERIVE_ID(6, 0x3f, 0x3f, 0x3f, 3)
	Generic Clock Generator 3 ID.
#define	CLOCK_MCHP_GCLKGEN_ID_GEN4   MCHP_CLOCK_DERIVE_ID(6, 0x3f, 0x3f, 0x3f, 4)
	Generic Clock Generator 4 ID.
#define	CLOCK_MCHP_GCLKGEN_ID_GEN5   MCHP_CLOCK_DERIVE_ID(6, 0x3f, 0x3f, 0x3f, 5)
	Generic Clock Generator 5 ID.
#define	CLOCK_MCHP_GCLKGEN_ID_GEN6   MCHP_CLOCK_DERIVE_ID(6, 0x3f, 0x3f, 0x3f, 6)
	Generic Clock Generator 6 ID.
#define	CLOCK_MCHP_GCLKGEN_ID_GEN7   MCHP_CLOCK_DERIVE_ID(6, 0x3f, 0x3f, 0x3f, 7)
	Generic Clock Generator 7 ID.
#define	CLOCK_MCHP_GCLKGEN_ID_GEN8   MCHP_CLOCK_DERIVE_ID(6, 0x3f, 0x3f, 0x3f, 8)
	Generic Clock Generator 8 ID.
#define	CLOCK_MCHP_GCLKGEN_ID_GEN9   MCHP_CLOCK_DERIVE_ID(6, 0x3f, 0x3f, 0x3f, 9)
	Generic Clock Generator 9 ID.
#define	CLOCK_MCHP_GCLKGEN_ID_GEN10   MCHP_CLOCK_DERIVE_ID(6, 0x3f, 0x3f, 0x3f, 10)
	Generic Clock Generator 10 ID.
#define	CLOCK_MCHP_GCLKGEN_ID_GEN11   MCHP_CLOCK_DERIVE_ID(6, 0x3f, 0x3f, 0x3f, 11)
	Generic Clock Generator 11 ID.
#define	CLOCK_MCHP_GCLKGEN_ID_MAX   (11)
	Maximum index for Generic Clock Generator IDs.
GCLKPERIPH_TYPE Clock IDs
#define	CLOCK_MCHP_GCLKPERIPH_ID_FREQM_MSR0   MCHP_CLOCK_DERIVE_ID(7, 0x3f, 0x3f, 2, 0)
	GCLK Peripheral ID: Frequency Meter Measure 0.
#define	CLOCK_MCHP_GCLKPERIPH_ID_FREQM_MSR1   MCHP_CLOCK_DERIVE_ID(7, 0x3f, 0x3f, 3, 1)
	GCLK Peripheral ID: Frequency Meter Measure 1.
#define	CLOCK_MCHP_GCLKPERIPH_ID_FREQM_REF   MCHP_CLOCK_DERIVE_ID(7, 0x3f, 0x3f, 4, 2)
	GCLK Peripheral ID: Frequency Meter Reference.
#define	CLOCK_MCHP_GCLKPERIPH_ID_EIC   MCHP_CLOCK_DERIVE_ID(7, 0x3f, 0x3f, 5, 3)
	GCLK Peripheral ID: External Interrupt Controller (EIC).
#define	CLOCK_MCHP_GCLKPERIPH_ID_CAN0   MCHP_CLOCK_DERIVE_ID(7, 0x3f, 0x3f, 6, 4)
	GCLK Peripheral ID: CAN0.
#define	CLOCK_MCHP_GCLKPERIPH_ID_CAN1   MCHP_CLOCK_DERIVE_ID(7, 0x3f, 0x3f, 7, 5)
	GCLK Peripheral ID: CAN1.
#define	CLOCK_MCHP_GCLKPERIPH_ID_EVSYS_CH0   MCHP_CLOCK_DERIVE_ID(7, 0x3f, 0x3f, 8, 6)
	GCLK Peripheral ID: Event System Channel 0.
#define	CLOCK_MCHP_GCLKPERIPH_ID_EVSYS_CH1   MCHP_CLOCK_DERIVE_ID(7, 0x3f, 0x3f, 9, 7)
	GCLK Peripheral ID: Event System Channel 1.
#define	CLOCK_MCHP_GCLKPERIPH_ID_EVSYS_CH2   MCHP_CLOCK_DERIVE_ID(7, 0x3f, 0x3f, 10, 8)
	GCLK Peripheral ID: Event System Channel 2.
#define	CLOCK_MCHP_GCLKPERIPH_ID_EVSYS_CH3   MCHP_CLOCK_DERIVE_ID(7, 0x3f, 0x3f, 11, 9)
	GCLK Peripheral ID: Event System Channel 3.
#define	CLOCK_MCHP_GCLKPERIPH_ID_EVSYS_CH4   MCHP_CLOCK_DERIVE_ID(7, 0x3f, 0x3f, 12, 10)
	GCLK Peripheral ID: Event System Channel 4.
#define	CLOCK_MCHP_GCLKPERIPH_ID_EVSYS_CH5   MCHP_CLOCK_DERIVE_ID(7, 0x3f, 0x3f, 13, 11)
	GCLK Peripheral ID: Event System Channel 5.
#define	CLOCK_MCHP_GCLKPERIPH_ID_EVSYS_CH6   MCHP_CLOCK_DERIVE_ID(7, 0x3f, 0x3f, 14, 12)
	GCLK Peripheral ID: Event System Channel 6.
#define	CLOCK_MCHP_GCLKPERIPH_ID_EVSYS_CH7   MCHP_CLOCK_DERIVE_ID(7, 0x3f, 0x3f, 15, 13)
	GCLK Peripheral ID: Event System Channel 7.
#define	CLOCK_MCHP_GCLKPERIPH_ID_EVSYS_CH8   MCHP_CLOCK_DERIVE_ID(7, 0x3f, 0x3f, 16, 14)
	GCLK Peripheral ID: Event System Channel 8.
#define	CLOCK_MCHP_GCLKPERIPH_ID_EVSYS_CH9   MCHP_CLOCK_DERIVE_ID(7, 0x3f, 0x3f, 17, 15)
	GCLK Peripheral ID: Event System Channel 9.
#define	CLOCK_MCHP_GCLKPERIPH_ID_EVSYS_CH10   MCHP_CLOCK_DERIVE_ID(7, 0x3f, 0x3f, 18, 16)
	GCLK Peripheral ID: Event System Channel 10.
#define	CLOCK_MCHP_GCLKPERIPH_ID_EVSYS_CH11   MCHP_CLOCK_DERIVE_ID(7, 0x3f, 0x3f, 19, 17)
	GCLK Peripheral ID: Event System Channel 11.
#define	CLOCK_MCHP_GCLKPERIPH_ID_SERCOM0_SLOW   MCHP_CLOCK_DERIVE_ID(7, 0x3f, 0x3f, 20, 18)
	GCLK Peripheral ID: SERCOM0 Slow clock.
#define	CLOCK_MCHP_GCLKPERIPH_ID_SERCOM1_SLOW   MCHP_CLOCK_DERIVE_ID(7, 0x3f, 0x3f, 20, 19)
	GCLK Peripheral ID: SERCOM1 Slow clock.
#define	CLOCK_MCHP_GCLKPERIPH_ID_SERCOM2_SLOW   MCHP_CLOCK_DERIVE_ID(7, 0x3f, 0x3f, 20, 20)
	GCLK Peripheral ID: SERCOM2 Slow clock.
#define	CLOCK_MCHP_GCLKPERIPH_ID_SERCOM3_SLOW   MCHP_CLOCK_DERIVE_ID(7, 0x3f, 0x3f, 20, 21)
	GCLK Peripheral ID: SERCOM3 Slow clock.
#define	CLOCK_MCHP_GCLKPERIPH_ID_SERCOM0_CORE   MCHP_CLOCK_DERIVE_ID(7, 0x3f, 0x3f, 21, 22)
	GCLK Peripheral ID: SERCOM0 Core clock.
#define	CLOCK_MCHP_GCLKPERIPH_ID_SERCOM1_CORE   MCHP_CLOCK_DERIVE_ID(7, 0x3f, 0x3f, 22, 23)
	GCLK Peripheral ID: SERCOM1 Core clock.
#define	CLOCK_MCHP_GCLKPERIPH_ID_SERCOM2_CORE   MCHP_CLOCK_DERIVE_ID(7, 0x3f, 0x3f, 23, 24)
	GCLK Peripheral ID: SERCOM2 Core clock.
#define	CLOCK_MCHP_GCLKPERIPH_ID_SERCOM3_CORE   MCHP_CLOCK_DERIVE_ID(7, 0x3f, 0x3f, 24, 25)
	GCLK Peripheral ID: SERCOM3 Core clock.
#define	CLOCK_MCHP_GCLKPERIPH_ID_TCC0   MCHP_CLOCK_DERIVE_ID(7, 0x3f, 0x3f, 25, 26)
	GCLK Peripheral ID: TCC0.
#define	CLOCK_MCHP_GCLKPERIPH_ID_TCC1   MCHP_CLOCK_DERIVE_ID(7, 0x3f, 0x3f, 25, 27)
	GCLK Peripheral ID: TCC1.
#define	CLOCK_MCHP_GCLKPERIPH_ID_TCC2   MCHP_CLOCK_DERIVE_ID(7, 0x3f, 0x3f, 26, 28)
	GCLK Peripheral ID: TCC2.
#define	CLOCK_MCHP_GCLKPERIPH_ID_TCC3   MCHP_CLOCK_DERIVE_ID(7, 0x3f, 0x3f, 27, 29)
	GCLK Peripheral ID: TCC3.
#define	CLOCK_MCHP_GCLKPERIPH_ID_SERCOM4_CORE   MCHP_CLOCK_DERIVE_ID(7, 0x3f, 0x3f, 28, 30)
	GCLK Peripheral ID: SERCOM4 Core clock.
#define	CLOCK_MCHP_GCLKPERIPH_ID_SERCOM5_CORE   MCHP_CLOCK_DERIVE_ID(7, 0x3f, 0x3f, 29, 31)
	GCLK Peripheral ID: SERCOM5 Core clock.
#define	CLOCK_MCHP_GCLKPERIPH_ID_TCC4   MCHP_CLOCK_DERIVE_ID(7, 0x3f, 0x3f, 30, 32)
	GCLK Peripheral ID: TCC4.
#define	CLOCK_MCHP_GCLKPERIPH_ID_TCC5   MCHP_CLOCK_DERIVE_ID(7, 0x3f, 0x3f, 31, 33)
	GCLK Peripheral ID: TCC5.
#define	CLOCK_MCHP_GCLKPERIPH_ID_TCC6   MCHP_CLOCK_DERIVE_ID(7, 0x3f, 0x3f, 32, 34)
	GCLK Peripheral ID: TCC6.
#define	CLOCK_MCHP_GCLKPERIPH_ID_ADC   MCHP_CLOCK_DERIVE_ID(7, 0x3f, 0x3f, 33, 35)
	GCLK Peripheral ID: ADC.
#define	CLOCK_MCHP_GCLKPERIPH_ID_AC   MCHP_CLOCK_DERIVE_ID(7, 0x3f, 0x3f, 34, 36)
	GCLK Peripheral ID: AC (Analog Comparator).
#define	CLOCK_MCHP_GCLKPERIPH_ID_PTC   MCHP_CLOCK_DERIVE_ID(7, 0x3f, 0x3f, 35, 37)
	GCLK Peripheral ID: PTC (Peripheral Touch Controller).
#define	CLOCK_MCHP_GCLKPERIPH_ID_CCL0   MCHP_CLOCK_DERIVE_ID(7, 0x3f, 0x3f, 36, 38)
	GCLK Peripheral ID: CCL0.
#define	CLOCK_MCHP_GCLKPERIPH_ID_CCL1   MCHP_CLOCK_DERIVE_ID(7, 0x3f, 0x3f, 37, 39)
	GCLK Peripheral ID: CCL1.
#define	CLOCK_MCHP_GCLKPERIPH_ID_USB   MCHP_CLOCK_DERIVE_ID(7, 0x3f, 0x3f, 38, 40)
	GCLK Peripheral ID: USB.
#define	CLOCK_MCHP_GCLKPERIPH_ID_MAX   (40)
	Maximum index for GCLK Peripheral IDs.
MCLKDOMAIN_TYPE Clock IDs
#define	CLOCK_MCHP_MCLKDOMAIN_ID_CPU   MCHP_CLOCK_DERIVE_ID(8, 0x3f, 0x3f, 0x3f, 0)
	Main Clock Domain ID: CPU.
#define	CLOCK_MCHP_MCLKDOMAIN_MAX   (0)
	Maximum index for Main Clock Domain IDs.
MCLKPERIPH_TYPE Clock IDs
#define	CLOCK_MCHP_MCLKPERIPH_ID_DSU_AHB   MCHP_CLOCK_DERIVE_ID(9, 0, 0, 0x3f, 0)
	MCLK Peripheral ID: DSU (AHB).
#define	CLOCK_MCHP_MCLKPERIPH_ID_FCR_AHB   MCHP_CLOCK_DERIVE_ID(9, 0, 1, 0x3f, 1)
	MCLK Peripheral ID: FCR (AHB).
#define	CLOCK_MCHP_MCLKPERIPH_ID_FCW_AHB   MCHP_CLOCK_DERIVE_ID(9, 0, 2, 0x3f, 2)
	MCLK Peripheral ID: FCW (AHB).
#define	CLOCK_MCHP_MCLKPERIPH_ID_PM   MCHP_CLOCK_DERIVE_ID(9, 0, 3, 0x3f, 3)
	MCLK Peripheral ID: PM.
#define	CLOCK_MCHP_MCLKPERIPH_ID_SUPC   MCHP_CLOCK_DERIVE_ID(9, 0, 4, 0x3f, 4)
	MCLK Peripheral ID: SUPC.
#define	CLOCK_MCHP_MCLKPERIPH_ID_RSTC   MCHP_CLOCK_DERIVE_ID(9, 0, 5, 0x3f, 5)
	MCLK Peripheral ID: RSTC.
#define	CLOCK_MCHP_MCLKPERIPH_ID_OSCCTRL   MCHP_CLOCK_DERIVE_ID(9, 0, 6, 0x3f, 6)
	MCLK Peripheral ID: OSCCTRL.
#define	CLOCK_MCHP_MCLKPERIPH_ID_OSC32KCTRL   MCHP_CLOCK_DERIVE_ID(9, 0, 7, 0x3f, 7)
	MCLK Peripheral ID: OSC32KCTRL.
#define	CLOCK_MCHP_MCLKPERIPH_ID_FREQM   MCHP_CLOCK_DERIVE_ID(9, 0, 10, 0x3f, 8)
	MCLK Peripheral ID: FREQM.
#define	CLOCK_MCHP_MCLKPERIPH_ID_WDT   MCHP_CLOCK_DERIVE_ID(9, 0, 11, 0x3f, 9)
	MCLK Peripheral ID: WDT.
#define	CLOCK_MCHP_MCLKPERIPH_ID_RTC   MCHP_CLOCK_DERIVE_ID(9, 0, 12, 0x3f, 10)
	MCLK Peripheral ID: RTC.
#define	CLOCK_MCHP_MCLKPERIPH_ID_EIC   MCHP_CLOCK_DERIVE_ID(9, 0, 13, 0x3f, 11)
	MCLK Peripheral ID: EIC.
#define	CLOCK_MCHP_MCLKPERIPH_ID_PAC_APB   MCHP_CLOCK_DERIVE_ID(9, 0, 14, 0x3f, 12)
	MCLK Peripheral ID: PAC (APB).
#define	CLOCK_MCHP_MCLKPERIPH_ID_TRAM   MCHP_CLOCK_DERIVE_ID(9, 0, 15, 0x3f, 13)
	MCLK Peripheral ID: TRAM.
#define	CLOCK_MCHP_MCLKPERIPH_ID_MCRAMC_APB   MCHP_CLOCK_DERIVE_ID(9, 0, 21, 0x3f, 14)
	MCLK Peripheral ID: MCRAMC_APB.
#define	CLOCK_MCHP_MCLKPERIPH_ID_MCRAMC_AHB   MCHP_CLOCK_DERIVE_ID(9, 0, 22, 0x3f, 15)
	MCLK Peripheral ID: MCRAMC_AHB.
#define	CLOCK_MCHP_MCLKPERIPH_ID_CAN0   MCHP_CLOCK_DERIVE_ID(9, 0, 23, 0x3f, 16)
	MCLK Peripheral ID: CAN0.
#define	CLOCK_MCHP_MCLKPERIPH_ID_CAN1   MCHP_CLOCK_DERIVE_ID(9, 0, 24, 0x3f, 17)
	MCLK Peripheral ID: CAN1.
#define	CLOCK_MCHP_MCLKPERIPH_ID_H2PB0_AHB   MCHP_CLOCK_DERIVE_ID(9, 0, 25, 0x3f, 18)
	MCLK Peripheral ID: H2PB0 (AHB).
#define	CLOCK_MCHP_MCLKPERIPH_ID_H2PB0_APB   MCHP_CLOCK_DERIVE_ID(9, 0, 26, 0x3f, 19)
	MCLK Peripheral ID: H2PB0 (APB).
#define	CLOCK_MCHP_MCLKPERIPH_ID_PORT_APB   MCHP_CLOCK_DERIVE_ID(9, 0, 27, 0x3f, 20)
	MCLK Peripheral ID: PORT (APB).
#define	CLOCK_MCHP_MCLKPERIPH_ID_DMAC_AHB   MCHP_CLOCK_DERIVE_ID(9, 0, 28, 0x3f, 21)
	MCLK Peripheral ID: DMAC (AHB).
#define	CLOCK_MCHP_MCLKPERIPH_ID_DMAC_APB   MCHP_CLOCK_DERIVE_ID(9, 0, 29, 0x3f, 22)
	MCLK Peripheral ID: DMAC (APB).
#define	CLOCK_MCHP_MCLKPERIPH_ID_HMATRIX2_AHB   MCHP_CLOCK_DERIVE_ID(9, 0, 30, 0x3f, 23)
	MCLK Peripheral ID: HMATRIX2 (AHB).
#define	CLOCK_MCHP_MCLKPERIPH_ID_HMATRIX2_APB   MCHP_CLOCK_DERIVE_ID(9, 0, 31, 0x3f, 24)
	MCLK Peripheral ID: HMATRIX2 (APB).
#define	CLOCK_MCHP_MCLKPERIPH_ID_BROMC_AHB   MCHP_CLOCK_DERIVE_ID(9, 1, 0, 0x3f, 25)
	MCLK Peripheral ID: BROMC (AHB).
#define	CLOCK_MCHP_MCLKPERIPH_ID_BROMC_APB   MCHP_CLOCK_DERIVE_ID(9, 1, 1, 0x3f, 26)
	MCLK Peripheral ID: BROMC (APB).
#define	CLOCK_MCHP_MCLKPERIPH_ID_IDAU   MCHP_CLOCK_DERIVE_ID(9, 1, 2, 0x3f, 27)
	MCLK Peripheral ID: IDAU.
#define	CLOCK_MCHP_MCLKPERIPH_ID_EVSYS   MCHP_CLOCK_DERIVE_ID(9, 1, 3, 0x3f, 28)
	MCLK Peripheral ID: EVSYS.
#define	CLOCK_MCHP_MCLKPERIPH_ID_SERCOM0   MCHP_CLOCK_DERIVE_ID(9, 1, 4, 0x3f, 29)
	MCLK Peripheral ID: SERCOM0.
#define	CLOCK_MCHP_MCLKPERIPH_ID_SERCOM1   MCHP_CLOCK_DERIVE_ID(9, 1, 5, 0x3f, 30)
	MCLK Peripheral ID: SERCOM1.
#define	CLOCK_MCHP_MCLKPERIPH_ID_SERCOM2   MCHP_CLOCK_DERIVE_ID(9, 1, 6, 0x3f, 31)
	MCLK Peripheral ID: SERCOM2.
#define	CLOCK_MCHP_MCLKPERIPH_ID_SERCOM3   MCHP_CLOCK_DERIVE_ID(9, 1, 7, 0x3f, 32)
	MCLK Peripheral ID: SERCOM3.
#define	CLOCK_MCHP_MCLKPERIPH_ID_TCC0   MCHP_CLOCK_DERIVE_ID(9, 1, 8, 0x3f, 33)
	MCLK Peripheral ID: TCC0.
#define	CLOCK_MCHP_MCLKPERIPH_ID_TCC1   MCHP_CLOCK_DERIVE_ID(9, 1, 9, 0x3f, 34)
	MCLK Peripheral ID: TCC1.
#define	CLOCK_MCHP_MCLKPERIPH_ID_TCC2   MCHP_CLOCK_DERIVE_ID(9, 1, 10, 0x3f, 35)
	MCLK Peripheral ID: TCC2.
#define	CLOCK_MCHP_MCLKPERIPH_ID_TCC3   MCHP_CLOCK_DERIVE_ID(9, 1, 11, 0x3f, 36)
	MCLK Peripheral ID: TCC3.
#define	CLOCK_MCHP_MCLKPERIPH_ID_SERCOM4   MCHP_CLOCK_DERIVE_ID(9, 1, 12, 0x3f, 37)
	MCLK Peripheral ID: SERCOM4.
#define	CLOCK_MCHP_MCLKPERIPH_ID_SERCOM5   MCHP_CLOCK_DERIVE_ID(9, 1, 13, 0x3f, 38)
	MCLK Peripheral ID: SERCOM5.
#define	CLOCK_MCHP_MCLKPERIPH_ID_TCC4   MCHP_CLOCK_DERIVE_ID(9, 1, 14, 0x3f, 39)
	MCLK Peripheral ID: TCC4.
#define	CLOCK_MCHP_MCLKPERIPH_ID_TCC5   MCHP_CLOCK_DERIVE_ID(9, 1, 15, 0x3f, 40)
	MCLK Peripheral ID: TCC5.
#define	CLOCK_MCHP_MCLKPERIPH_ID_TCC6   MCHP_CLOCK_DERIVE_ID(9, 1, 16, 0x3f, 41)
	MCLK Peripheral ID: TCC6.
#define	CLOCK_MCHP_MCLKPERIPH_ID_ADC   MCHP_CLOCK_DERIVE_ID(9, 1, 17, 0x3f, 42)
	MCLK Peripheral ID: ADC.
#define	CLOCK_MCHP_MCLKPERIPH_ID_AC   MCHP_CLOCK_DERIVE_ID(9, 1, 18, 0x3f, 43)
	MCLK Peripheral ID: AC.
#define	CLOCK_MCHP_MCLKPERIPH_ID_PTC   MCHP_CLOCK_DERIVE_ID(9, 1, 19, 0x3f, 44)
	MCLK Peripheral ID: PTC.
#define	CLOCK_MCHP_MCLKPERIPH_ID_CCL0   MCHP_CLOCK_DERIVE_ID(9, 1, 20, 0x3f, 45)
	MCLK Peripheral ID: CCL0.
#define	CLOCK_MCHP_MCLKPERIPH_ID_CCL1   MCHP_CLOCK_DERIVE_ID(9, 1, 21, 0x3f, 46)
	MCLK Peripheral ID: CCL1.
#define	CLOCK_MCHP_MCLKPERIPH_ID_USB_AHB   MCHP_CLOCK_DERIVE_ID(9, 1, 22, 0x3f, 47)
	MCLK Peripheral ID: USB_AHB.
#define	CLOCK_MCHP_MCLKPERIPH_ID_USB_APB   MCHP_CLOCK_DERIVE_ID(9, 1, 23, 0x3f, 48)
	MCLK Peripheral ID: USB_APB.
#define	CLOCK_MCHP_MCLKPERIPH_ID_AT   MCHP_CLOCK_DERIVE_ID(9, 1, 24, 0x3f, 49)
	MCLK Peripheral ID: AT.
#define	CLOCK_MCHP_MCLKPERIPH_ID_H2PB1_AHB   MCHP_CLOCK_DERIVE_ID(9, 1, 25, 0x3f, 50)
	MCLK Peripheral ID: H2PB1_AHB.
#define	CLOCK_MCHP_MCLKPERIPH_ID_H2PB1_APB   MCHP_CLOCK_DERIVE_ID(9, 1, 26, 0x3f, 51)
	MCLK Peripheral ID: H2PB1_APB.
#define	CLOCK_MCHP_MCLKPERIPH_ID_H2PB2_AHB   MCHP_CLOCK_DERIVE_ID(9, 1, 27, 0x3f, 52)
	MCLK Peripheral ID: H2PB2_AHB.
#define	CLOCK_MCHP_MCLKPERIPH_ID_H2PB2_APB   MCHP_CLOCK_DERIVE_ID(9, 1, 28, 0x3f, 53)
	MCLK Peripheral ID: H2PB2_APB.
#define	CLOCK_MCHP_MCLKPERIPH_ID_HSM   MCHP_CLOCK_DERIVE_ID(9, 1, 30, 0x3f, 54)
	MCLK Peripheral ID: HSM.
#define	CLOCK_MCHP_MCLKPERIPH_ID_PUF   MCHP_CLOCK_DERIVE_ID(9, 1, 31, 0x3f, 55)
	MCLK Peripheral ID: PUF.
#define	CLOCK_MCHP_MCLKPERIPH_ID_MAX   (55)
	Maximum index for MCLK Peripheral IDs.

Detailed Description

List clock subsystem IDs for pic32cm_sg_gc family.

Clock subsystem IDs. To be used in devicetree nodes, and as argument for clock API.

Macro Definition Documentation

CLOCK_MCHP_DFLL48M_ID

#define CLOCK_MCHP_DFLL48M_ID   MCHP_CLOCK_DERIVE_ID(1, 0x3f, 0x3f, 0, 0)

DFLL48M (48 MHz Digital Frequency Locked Loop) clock ID.

CLOCK_MCHP_DFLL48M_ID_MAX

#define CLOCK_MCHP_DFLL48M_ID_MAX   (0)

Maximum index for DFLL48M clock IDs.

CLOCK_MCHP_DPLL0_ID_OUT0

#define CLOCK_MCHP_DPLL0_ID_OUT0   MCHP_CLOCK_DERIVE_ID(3, 0x3f, 0x3f, 0x3f, 0)

DPLL0 Output 0 clock ID.

CLOCK_MCHP_DPLL0_ID_OUT1

#define CLOCK_MCHP_DPLL0_ID_OUT1   MCHP_CLOCK_DERIVE_ID(3, 0x3f, 0x3f, 0x3f, 1)

DPLL0 Output 1 clock ID.

CLOCK_MCHP_DPLL0_ID_OUT2

#define CLOCK_MCHP_DPLL0_ID_OUT2   MCHP_CLOCK_DERIVE_ID(3, 0x3f, 0x3f, 0x3f, 2)

DPLL0 Output 2 clock ID.

CLOCK_MCHP_DPLL0_ID_OUT3

#define CLOCK_MCHP_DPLL0_ID_OUT3   MCHP_CLOCK_DERIVE_ID(3, 0x3f, 0x3f, 0x3f, 3)

DPLL0 Output 3 clock ID.

CLOCK_MCHP_DPLL0_ID_OUT4

#define CLOCK_MCHP_DPLL0_ID_OUT4   MCHP_CLOCK_DERIVE_ID(3, 0x3f, 0x3f, 0x3f, 4)

DPLL0 Output 4 clock ID.

CLOCK_MCHP_DPLL_ID_DPLL0

#define CLOCK_MCHP_DPLL_ID_DPLL0   MCHP_CLOCK_DERIVE_ID(2, 0x3f, 0x3f, 1, 0)

DPLL0 clock ID.

CLOCK_MCHP_DPLL_ID_MAX

#define CLOCK_MCHP_DPLL_ID_MAX   (0)

Maximum index for DPLL clock IDs.

CLOCK_MCHP_DPLL_OUT_ID_MAX

#define CLOCK_MCHP_DPLL_OUT_ID_MAX   (4)

Maximum index for DPLL output clock IDs.

CLOCK_MCHP_GCLKGEN_ID_GEN0

#define CLOCK_MCHP_GCLKGEN_ID_GEN0   MCHP_CLOCK_DERIVE_ID(6, 0x3f, 0x3f, 0x3f, 0)

Generic Clock Generator 0 ID.

CLOCK_MCHP_GCLKGEN_ID_GEN1

#define CLOCK_MCHP_GCLKGEN_ID_GEN1   MCHP_CLOCK_DERIVE_ID(6, 0x3f, 0x3f, 0x3f, 1)

Generic Clock Generator 1 ID.

CLOCK_MCHP_GCLKGEN_ID_GEN10

#define CLOCK_MCHP_GCLKGEN_ID_GEN10   MCHP_CLOCK_DERIVE_ID(6, 0x3f, 0x3f, 0x3f, 10)

Generic Clock Generator 10 ID.

CLOCK_MCHP_GCLKGEN_ID_GEN11

#define CLOCK_MCHP_GCLKGEN_ID_GEN11   MCHP_CLOCK_DERIVE_ID(6, 0x3f, 0x3f, 0x3f, 11)

Generic Clock Generator 11 ID.

CLOCK_MCHP_GCLKGEN_ID_GEN2

#define CLOCK_MCHP_GCLKGEN_ID_GEN2   MCHP_CLOCK_DERIVE_ID(6, 0x3f, 0x3f, 0x3f, 2)

Generic Clock Generator 2 ID.

CLOCK_MCHP_GCLKGEN_ID_GEN3

#define CLOCK_MCHP_GCLKGEN_ID_GEN3   MCHP_CLOCK_DERIVE_ID(6, 0x3f, 0x3f, 0x3f, 3)

Generic Clock Generator 3 ID.

CLOCK_MCHP_GCLKGEN_ID_GEN4

#define CLOCK_MCHP_GCLKGEN_ID_GEN4   MCHP_CLOCK_DERIVE_ID(6, 0x3f, 0x3f, 0x3f, 4)

Generic Clock Generator 4 ID.

CLOCK_MCHP_GCLKGEN_ID_GEN5

#define CLOCK_MCHP_GCLKGEN_ID_GEN5   MCHP_CLOCK_DERIVE_ID(6, 0x3f, 0x3f, 0x3f, 5)

Generic Clock Generator 5 ID.

CLOCK_MCHP_GCLKGEN_ID_GEN6

#define CLOCK_MCHP_GCLKGEN_ID_GEN6   MCHP_CLOCK_DERIVE_ID(6, 0x3f, 0x3f, 0x3f, 6)

Generic Clock Generator 6 ID.

CLOCK_MCHP_GCLKGEN_ID_GEN7

#define CLOCK_MCHP_GCLKGEN_ID_GEN7   MCHP_CLOCK_DERIVE_ID(6, 0x3f, 0x3f, 0x3f, 7)

Generic Clock Generator 7 ID.

CLOCK_MCHP_GCLKGEN_ID_GEN8

#define CLOCK_MCHP_GCLKGEN_ID_GEN8   MCHP_CLOCK_DERIVE_ID(6, 0x3f, 0x3f, 0x3f, 8)

Generic Clock Generator 8 ID.

CLOCK_MCHP_GCLKGEN_ID_GEN9

#define CLOCK_MCHP_GCLKGEN_ID_GEN9   MCHP_CLOCK_DERIVE_ID(6, 0x3f, 0x3f, 0x3f, 9)

Generic Clock Generator 9 ID.

CLOCK_MCHP_GCLKGEN_ID_MAX

#define CLOCK_MCHP_GCLKGEN_ID_MAX   (11)

Maximum index for Generic Clock Generator IDs.

CLOCK_MCHP_GCLKPERIPH_ID_AC

#define CLOCK_MCHP_GCLKPERIPH_ID_AC   MCHP_CLOCK_DERIVE_ID(7, 0x3f, 0x3f, 34, 36)

GCLK Peripheral ID: AC (Analog Comparator).

CLOCK_MCHP_GCLKPERIPH_ID_ADC

#define CLOCK_MCHP_GCLKPERIPH_ID_ADC   MCHP_CLOCK_DERIVE_ID(7, 0x3f, 0x3f, 33, 35)

GCLK Peripheral ID: ADC.

CLOCK_MCHP_GCLKPERIPH_ID_CAN0

#define CLOCK_MCHP_GCLKPERIPH_ID_CAN0   MCHP_CLOCK_DERIVE_ID(7, 0x3f, 0x3f, 6, 4)

GCLK Peripheral ID: CAN0.

CLOCK_MCHP_GCLKPERIPH_ID_CAN1

#define CLOCK_MCHP_GCLKPERIPH_ID_CAN1   MCHP_CLOCK_DERIVE_ID(7, 0x3f, 0x3f, 7, 5)

GCLK Peripheral ID: CAN1.

CLOCK_MCHP_GCLKPERIPH_ID_CCL0

#define CLOCK_MCHP_GCLKPERIPH_ID_CCL0   MCHP_CLOCK_DERIVE_ID(7, 0x3f, 0x3f, 36, 38)

GCLK Peripheral ID: CCL0.

CLOCK_MCHP_GCLKPERIPH_ID_CCL1

#define CLOCK_MCHP_GCLKPERIPH_ID_CCL1   MCHP_CLOCK_DERIVE_ID(7, 0x3f, 0x3f, 37, 39)

GCLK Peripheral ID: CCL1.

CLOCK_MCHP_GCLKPERIPH_ID_EIC

#define CLOCK_MCHP_GCLKPERIPH_ID_EIC   MCHP_CLOCK_DERIVE_ID(7, 0x3f, 0x3f, 5, 3)

GCLK Peripheral ID: External Interrupt Controller (EIC).

CLOCK_MCHP_GCLKPERIPH_ID_EVSYS_CH0

#define CLOCK_MCHP_GCLKPERIPH_ID_EVSYS_CH0   MCHP_CLOCK_DERIVE_ID(7, 0x3f, 0x3f, 8, 6)

GCLK Peripheral ID: Event System Channel 0.

CLOCK_MCHP_GCLKPERIPH_ID_EVSYS_CH1

#define CLOCK_MCHP_GCLKPERIPH_ID_EVSYS_CH1   MCHP_CLOCK_DERIVE_ID(7, 0x3f, 0x3f, 9, 7)

GCLK Peripheral ID: Event System Channel 1.

CLOCK_MCHP_GCLKPERIPH_ID_EVSYS_CH10

#define CLOCK_MCHP_GCLKPERIPH_ID_EVSYS_CH10   MCHP_CLOCK_DERIVE_ID(7, 0x3f, 0x3f, 18, 16)

GCLK Peripheral ID: Event System Channel 10.

CLOCK_MCHP_GCLKPERIPH_ID_EVSYS_CH11

#define CLOCK_MCHP_GCLKPERIPH_ID_EVSYS_CH11   MCHP_CLOCK_DERIVE_ID(7, 0x3f, 0x3f, 19, 17)

GCLK Peripheral ID: Event System Channel 11.

CLOCK_MCHP_GCLKPERIPH_ID_EVSYS_CH2

#define CLOCK_MCHP_GCLKPERIPH_ID_EVSYS_CH2   MCHP_CLOCK_DERIVE_ID(7, 0x3f, 0x3f, 10, 8)

GCLK Peripheral ID: Event System Channel 2.

CLOCK_MCHP_GCLKPERIPH_ID_EVSYS_CH3

#define CLOCK_MCHP_GCLKPERIPH_ID_EVSYS_CH3   MCHP_CLOCK_DERIVE_ID(7, 0x3f, 0x3f, 11, 9)

GCLK Peripheral ID: Event System Channel 3.

CLOCK_MCHP_GCLKPERIPH_ID_EVSYS_CH4

#define CLOCK_MCHP_GCLKPERIPH_ID_EVSYS_CH4   MCHP_CLOCK_DERIVE_ID(7, 0x3f, 0x3f, 12, 10)

GCLK Peripheral ID: Event System Channel 4.

CLOCK_MCHP_GCLKPERIPH_ID_EVSYS_CH5

#define CLOCK_MCHP_GCLKPERIPH_ID_EVSYS_CH5   MCHP_CLOCK_DERIVE_ID(7, 0x3f, 0x3f, 13, 11)

GCLK Peripheral ID: Event System Channel 5.

CLOCK_MCHP_GCLKPERIPH_ID_EVSYS_CH6

#define CLOCK_MCHP_GCLKPERIPH_ID_EVSYS_CH6   MCHP_CLOCK_DERIVE_ID(7, 0x3f, 0x3f, 14, 12)

GCLK Peripheral ID: Event System Channel 6.

CLOCK_MCHP_GCLKPERIPH_ID_EVSYS_CH7

#define CLOCK_MCHP_GCLKPERIPH_ID_EVSYS_CH7   MCHP_CLOCK_DERIVE_ID(7, 0x3f, 0x3f, 15, 13)

GCLK Peripheral ID: Event System Channel 7.

CLOCK_MCHP_GCLKPERIPH_ID_EVSYS_CH8

#define CLOCK_MCHP_GCLKPERIPH_ID_EVSYS_CH8   MCHP_CLOCK_DERIVE_ID(7, 0x3f, 0x3f, 16, 14)

GCLK Peripheral ID: Event System Channel 8.

CLOCK_MCHP_GCLKPERIPH_ID_EVSYS_CH9

#define CLOCK_MCHP_GCLKPERIPH_ID_EVSYS_CH9   MCHP_CLOCK_DERIVE_ID(7, 0x3f, 0x3f, 17, 15)

GCLK Peripheral ID: Event System Channel 9.

CLOCK_MCHP_GCLKPERIPH_ID_FREQM_MSR0

#define CLOCK_MCHP_GCLKPERIPH_ID_FREQM_MSR0   MCHP_CLOCK_DERIVE_ID(7, 0x3f, 0x3f, 2, 0)

GCLK Peripheral ID: Frequency Meter Measure 0.

CLOCK_MCHP_GCLKPERIPH_ID_FREQM_MSR1

#define CLOCK_MCHP_GCLKPERIPH_ID_FREQM_MSR1   MCHP_CLOCK_DERIVE_ID(7, 0x3f, 0x3f, 3, 1)

GCLK Peripheral ID: Frequency Meter Measure 1.

CLOCK_MCHP_GCLKPERIPH_ID_FREQM_REF

#define CLOCK_MCHP_GCLKPERIPH_ID_FREQM_REF   MCHP_CLOCK_DERIVE_ID(7, 0x3f, 0x3f, 4, 2)

GCLK Peripheral ID: Frequency Meter Reference.

CLOCK_MCHP_GCLKPERIPH_ID_MAX

#define CLOCK_MCHP_GCLKPERIPH_ID_MAX   (40)

Maximum index for GCLK Peripheral IDs.

CLOCK_MCHP_GCLKPERIPH_ID_PTC

#define CLOCK_MCHP_GCLKPERIPH_ID_PTC   MCHP_CLOCK_DERIVE_ID(7, 0x3f, 0x3f, 35, 37)

GCLK Peripheral ID: PTC (Peripheral Touch Controller).

CLOCK_MCHP_GCLKPERIPH_ID_SERCOM0_CORE

#define CLOCK_MCHP_GCLKPERIPH_ID_SERCOM0_CORE   MCHP_CLOCK_DERIVE_ID(7, 0x3f, 0x3f, 21, 22)

GCLK Peripheral ID: SERCOM0 Core clock.

CLOCK_MCHP_GCLKPERIPH_ID_SERCOM0_SLOW

#define CLOCK_MCHP_GCLKPERIPH_ID_SERCOM0_SLOW   MCHP_CLOCK_DERIVE_ID(7, 0x3f, 0x3f, 20, 18)

GCLK Peripheral ID: SERCOM0 Slow clock.

CLOCK_MCHP_GCLKPERIPH_ID_SERCOM1_CORE

#define CLOCK_MCHP_GCLKPERIPH_ID_SERCOM1_CORE   MCHP_CLOCK_DERIVE_ID(7, 0x3f, 0x3f, 22, 23)

GCLK Peripheral ID: SERCOM1 Core clock.

CLOCK_MCHP_GCLKPERIPH_ID_SERCOM1_SLOW

#define CLOCK_MCHP_GCLKPERIPH_ID_SERCOM1_SLOW   MCHP_CLOCK_DERIVE_ID(7, 0x3f, 0x3f, 20, 19)

GCLK Peripheral ID: SERCOM1 Slow clock.

CLOCK_MCHP_GCLKPERIPH_ID_SERCOM2_CORE

#define CLOCK_MCHP_GCLKPERIPH_ID_SERCOM2_CORE   MCHP_CLOCK_DERIVE_ID(7, 0x3f, 0x3f, 23, 24)

GCLK Peripheral ID: SERCOM2 Core clock.

CLOCK_MCHP_GCLKPERIPH_ID_SERCOM2_SLOW

#define CLOCK_MCHP_GCLKPERIPH_ID_SERCOM2_SLOW   MCHP_CLOCK_DERIVE_ID(7, 0x3f, 0x3f, 20, 20)

GCLK Peripheral ID: SERCOM2 Slow clock.

CLOCK_MCHP_GCLKPERIPH_ID_SERCOM3_CORE

#define CLOCK_MCHP_GCLKPERIPH_ID_SERCOM3_CORE   MCHP_CLOCK_DERIVE_ID(7, 0x3f, 0x3f, 24, 25)

GCLK Peripheral ID: SERCOM3 Core clock.

CLOCK_MCHP_GCLKPERIPH_ID_SERCOM3_SLOW

#define CLOCK_MCHP_GCLKPERIPH_ID_SERCOM3_SLOW   MCHP_CLOCK_DERIVE_ID(7, 0x3f, 0x3f, 20, 21)

GCLK Peripheral ID: SERCOM3 Slow clock.

CLOCK_MCHP_GCLKPERIPH_ID_SERCOM4_CORE

#define CLOCK_MCHP_GCLKPERIPH_ID_SERCOM4_CORE   MCHP_CLOCK_DERIVE_ID(7, 0x3f, 0x3f, 28, 30)

GCLK Peripheral ID: SERCOM4 Core clock.

CLOCK_MCHP_GCLKPERIPH_ID_SERCOM5_CORE

#define CLOCK_MCHP_GCLKPERIPH_ID_SERCOM5_CORE   MCHP_CLOCK_DERIVE_ID(7, 0x3f, 0x3f, 29, 31)

GCLK Peripheral ID: SERCOM5 Core clock.

CLOCK_MCHP_GCLKPERIPH_ID_TCC0

#define CLOCK_MCHP_GCLKPERIPH_ID_TCC0   MCHP_CLOCK_DERIVE_ID(7, 0x3f, 0x3f, 25, 26)

GCLK Peripheral ID: TCC0.

CLOCK_MCHP_GCLKPERIPH_ID_TCC1

#define CLOCK_MCHP_GCLKPERIPH_ID_TCC1   MCHP_CLOCK_DERIVE_ID(7, 0x3f, 0x3f, 25, 27)

GCLK Peripheral ID: TCC1.

CLOCK_MCHP_GCLKPERIPH_ID_TCC2

#define CLOCK_MCHP_GCLKPERIPH_ID_TCC2   MCHP_CLOCK_DERIVE_ID(7, 0x3f, 0x3f, 26, 28)

GCLK Peripheral ID: TCC2.

CLOCK_MCHP_GCLKPERIPH_ID_TCC3

#define CLOCK_MCHP_GCLKPERIPH_ID_TCC3   MCHP_CLOCK_DERIVE_ID(7, 0x3f, 0x3f, 27, 29)

GCLK Peripheral ID: TCC3.

CLOCK_MCHP_GCLKPERIPH_ID_TCC4

#define CLOCK_MCHP_GCLKPERIPH_ID_TCC4   MCHP_CLOCK_DERIVE_ID(7, 0x3f, 0x3f, 30, 32)

GCLK Peripheral ID: TCC4.

CLOCK_MCHP_GCLKPERIPH_ID_TCC5

#define CLOCK_MCHP_GCLKPERIPH_ID_TCC5   MCHP_CLOCK_DERIVE_ID(7, 0x3f, 0x3f, 31, 33)

GCLK Peripheral ID: TCC5.

CLOCK_MCHP_GCLKPERIPH_ID_TCC6

#define CLOCK_MCHP_GCLKPERIPH_ID_TCC6   MCHP_CLOCK_DERIVE_ID(7, 0x3f, 0x3f, 32, 34)

GCLK Peripheral ID: TCC6.

CLOCK_MCHP_GCLKPERIPH_ID_USB

#define CLOCK_MCHP_GCLKPERIPH_ID_USB   MCHP_CLOCK_DERIVE_ID(7, 0x3f, 0x3f, 38, 40)

GCLK Peripheral ID: USB.

CLOCK_MCHP_MCLKDOMAIN_ID_CPU

#define CLOCK_MCHP_MCLKDOMAIN_ID_CPU   MCHP_CLOCK_DERIVE_ID(8, 0x3f, 0x3f, 0x3f, 0)

Main Clock Domain ID: CPU.

CLOCK_MCHP_MCLKDOMAIN_MAX

#define CLOCK_MCHP_MCLKDOMAIN_MAX   (0)

Maximum index for Main Clock Domain IDs.

CLOCK_MCHP_MCLKPERIPH_ID_AC

#define CLOCK_MCHP_MCLKPERIPH_ID_AC   MCHP_CLOCK_DERIVE_ID(9, 1, 18, 0x3f, 43)

MCLK Peripheral ID: AC.

CLOCK_MCHP_MCLKPERIPH_ID_ADC

#define CLOCK_MCHP_MCLKPERIPH_ID_ADC   MCHP_CLOCK_DERIVE_ID(9, 1, 17, 0x3f, 42)

MCLK Peripheral ID: ADC.

CLOCK_MCHP_MCLKPERIPH_ID_AT

#define CLOCK_MCHP_MCLKPERIPH_ID_AT   MCHP_CLOCK_DERIVE_ID(9, 1, 24, 0x3f, 49)

MCLK Peripheral ID: AT.

CLOCK_MCHP_MCLKPERIPH_ID_BROMC_AHB

#define CLOCK_MCHP_MCLKPERIPH_ID_BROMC_AHB   MCHP_CLOCK_DERIVE_ID(9, 1, 0, 0x3f, 25)

MCLK Peripheral ID: BROMC (AHB).

CLOCK_MCHP_MCLKPERIPH_ID_BROMC_APB

#define CLOCK_MCHP_MCLKPERIPH_ID_BROMC_APB   MCHP_CLOCK_DERIVE_ID(9, 1, 1, 0x3f, 26)

MCLK Peripheral ID: BROMC (APB).

CLOCK_MCHP_MCLKPERIPH_ID_CAN0

#define CLOCK_MCHP_MCLKPERIPH_ID_CAN0   MCHP_CLOCK_DERIVE_ID(9, 0, 23, 0x3f, 16)

MCLK Peripheral ID: CAN0.

CLOCK_MCHP_MCLKPERIPH_ID_CAN1

#define CLOCK_MCHP_MCLKPERIPH_ID_CAN1   MCHP_CLOCK_DERIVE_ID(9, 0, 24, 0x3f, 17)

MCLK Peripheral ID: CAN1.

CLOCK_MCHP_MCLKPERIPH_ID_CCL0

#define CLOCK_MCHP_MCLKPERIPH_ID_CCL0   MCHP_CLOCK_DERIVE_ID(9, 1, 20, 0x3f, 45)

MCLK Peripheral ID: CCL0.

CLOCK_MCHP_MCLKPERIPH_ID_CCL1

#define CLOCK_MCHP_MCLKPERIPH_ID_CCL1   MCHP_CLOCK_DERIVE_ID(9, 1, 21, 0x3f, 46)

MCLK Peripheral ID: CCL1.

CLOCK_MCHP_MCLKPERIPH_ID_DMAC_AHB

#define CLOCK_MCHP_MCLKPERIPH_ID_DMAC_AHB   MCHP_CLOCK_DERIVE_ID(9, 0, 28, 0x3f, 21)

MCLK Peripheral ID: DMAC (AHB).

CLOCK_MCHP_MCLKPERIPH_ID_DMAC_APB

#define CLOCK_MCHP_MCLKPERIPH_ID_DMAC_APB   MCHP_CLOCK_DERIVE_ID(9, 0, 29, 0x3f, 22)

MCLK Peripheral ID: DMAC (APB).

CLOCK_MCHP_MCLKPERIPH_ID_DSU_AHB

#define CLOCK_MCHP_MCLKPERIPH_ID_DSU_AHB   MCHP_CLOCK_DERIVE_ID(9, 0, 0, 0x3f, 0)

MCLK Peripheral ID: DSU (AHB).

CLOCK_MCHP_MCLKPERIPH_ID_EIC

#define CLOCK_MCHP_MCLKPERIPH_ID_EIC   MCHP_CLOCK_DERIVE_ID(9, 0, 13, 0x3f, 11)

MCLK Peripheral ID: EIC.

CLOCK_MCHP_MCLKPERIPH_ID_EVSYS

#define CLOCK_MCHP_MCLKPERIPH_ID_EVSYS   MCHP_CLOCK_DERIVE_ID(9, 1, 3, 0x3f, 28)

MCLK Peripheral ID: EVSYS.

CLOCK_MCHP_MCLKPERIPH_ID_FCR_AHB

#define CLOCK_MCHP_MCLKPERIPH_ID_FCR_AHB   MCHP_CLOCK_DERIVE_ID(9, 0, 1, 0x3f, 1)

MCLK Peripheral ID: FCR (AHB).

CLOCK_MCHP_MCLKPERIPH_ID_FCW_AHB

#define CLOCK_MCHP_MCLKPERIPH_ID_FCW_AHB   MCHP_CLOCK_DERIVE_ID(9, 0, 2, 0x3f, 2)

MCLK Peripheral ID: FCW (AHB).

CLOCK_MCHP_MCLKPERIPH_ID_FREQM

#define CLOCK_MCHP_MCLKPERIPH_ID_FREQM   MCHP_CLOCK_DERIVE_ID(9, 0, 10, 0x3f, 8)

MCLK Peripheral ID: FREQM.

CLOCK_MCHP_MCLKPERIPH_ID_H2PB0_AHB

#define CLOCK_MCHP_MCLKPERIPH_ID_H2PB0_AHB   MCHP_CLOCK_DERIVE_ID(9, 0, 25, 0x3f, 18)

MCLK Peripheral ID: H2PB0 (AHB).

CLOCK_MCHP_MCLKPERIPH_ID_H2PB0_APB

#define CLOCK_MCHP_MCLKPERIPH_ID_H2PB0_APB   MCHP_CLOCK_DERIVE_ID(9, 0, 26, 0x3f, 19)

MCLK Peripheral ID: H2PB0 (APB).

CLOCK_MCHP_MCLKPERIPH_ID_H2PB1_AHB

#define CLOCK_MCHP_MCLKPERIPH_ID_H2PB1_AHB   MCHP_CLOCK_DERIVE_ID(9, 1, 25, 0x3f, 50)

MCLK Peripheral ID: H2PB1_AHB.

CLOCK_MCHP_MCLKPERIPH_ID_H2PB1_APB

#define CLOCK_MCHP_MCLKPERIPH_ID_H2PB1_APB   MCHP_CLOCK_DERIVE_ID(9, 1, 26, 0x3f, 51)

MCLK Peripheral ID: H2PB1_APB.

CLOCK_MCHP_MCLKPERIPH_ID_H2PB2_AHB

#define CLOCK_MCHP_MCLKPERIPH_ID_H2PB2_AHB   MCHP_CLOCK_DERIVE_ID(9, 1, 27, 0x3f, 52)

MCLK Peripheral ID: H2PB2_AHB.

CLOCK_MCHP_MCLKPERIPH_ID_H2PB2_APB

#define CLOCK_MCHP_MCLKPERIPH_ID_H2PB2_APB   MCHP_CLOCK_DERIVE_ID(9, 1, 28, 0x3f, 53)

MCLK Peripheral ID: H2PB2_APB.

CLOCK_MCHP_MCLKPERIPH_ID_HMATRIX2_AHB

#define CLOCK_MCHP_MCLKPERIPH_ID_HMATRIX2_AHB   MCHP_CLOCK_DERIVE_ID(9, 0, 30, 0x3f, 23)

MCLK Peripheral ID: HMATRIX2 (AHB).

CLOCK_MCHP_MCLKPERIPH_ID_HMATRIX2_APB

#define CLOCK_MCHP_MCLKPERIPH_ID_HMATRIX2_APB   MCHP_CLOCK_DERIVE_ID(9, 0, 31, 0x3f, 24)

MCLK Peripheral ID: HMATRIX2 (APB).

CLOCK_MCHP_MCLKPERIPH_ID_HSM

#define CLOCK_MCHP_MCLKPERIPH_ID_HSM   MCHP_CLOCK_DERIVE_ID(9, 1, 30, 0x3f, 54)

MCLK Peripheral ID: HSM.

CLOCK_MCHP_MCLKPERIPH_ID_IDAU

#define CLOCK_MCHP_MCLKPERIPH_ID_IDAU   MCHP_CLOCK_DERIVE_ID(9, 1, 2, 0x3f, 27)

MCLK Peripheral ID: IDAU.

CLOCK_MCHP_MCLKPERIPH_ID_MAX

#define CLOCK_MCHP_MCLKPERIPH_ID_MAX   (55)

Maximum index for MCLK Peripheral IDs.

CLOCK_MCHP_MCLKPERIPH_ID_MCRAMC_AHB

#define CLOCK_MCHP_MCLKPERIPH_ID_MCRAMC_AHB   MCHP_CLOCK_DERIVE_ID(9, 0, 22, 0x3f, 15)

MCLK Peripheral ID: MCRAMC_AHB.

CLOCK_MCHP_MCLKPERIPH_ID_MCRAMC_APB

#define CLOCK_MCHP_MCLKPERIPH_ID_MCRAMC_APB   MCHP_CLOCK_DERIVE_ID(9, 0, 21, 0x3f, 14)

MCLK Peripheral ID: MCRAMC_APB.

CLOCK_MCHP_MCLKPERIPH_ID_OSC32KCTRL

#define CLOCK_MCHP_MCLKPERIPH_ID_OSC32KCTRL   MCHP_CLOCK_DERIVE_ID(9, 0, 7, 0x3f, 7)

MCLK Peripheral ID: OSC32KCTRL.

CLOCK_MCHP_MCLKPERIPH_ID_OSCCTRL

#define CLOCK_MCHP_MCLKPERIPH_ID_OSCCTRL   MCHP_CLOCK_DERIVE_ID(9, 0, 6, 0x3f, 6)

MCLK Peripheral ID: OSCCTRL.

CLOCK_MCHP_MCLKPERIPH_ID_PAC_APB

#define CLOCK_MCHP_MCLKPERIPH_ID_PAC_APB   MCHP_CLOCK_DERIVE_ID(9, 0, 14, 0x3f, 12)

MCLK Peripheral ID: PAC (APB).

CLOCK_MCHP_MCLKPERIPH_ID_PM

#define CLOCK_MCHP_MCLKPERIPH_ID_PM   MCHP_CLOCK_DERIVE_ID(9, 0, 3, 0x3f, 3)

MCLK Peripheral ID: PM.

CLOCK_MCHP_MCLKPERIPH_ID_PORT_APB

#define CLOCK_MCHP_MCLKPERIPH_ID_PORT_APB   MCHP_CLOCK_DERIVE_ID(9, 0, 27, 0x3f, 20)

MCLK Peripheral ID: PORT (APB).

CLOCK_MCHP_MCLKPERIPH_ID_PTC

#define CLOCK_MCHP_MCLKPERIPH_ID_PTC   MCHP_CLOCK_DERIVE_ID(9, 1, 19, 0x3f, 44)

MCLK Peripheral ID: PTC.

CLOCK_MCHP_MCLKPERIPH_ID_PUF

#define CLOCK_MCHP_MCLKPERIPH_ID_PUF   MCHP_CLOCK_DERIVE_ID(9, 1, 31, 0x3f, 55)

MCLK Peripheral ID: PUF.

CLOCK_MCHP_MCLKPERIPH_ID_RSTC

#define CLOCK_MCHP_MCLKPERIPH_ID_RSTC   MCHP_CLOCK_DERIVE_ID(9, 0, 5, 0x3f, 5)

MCLK Peripheral ID: RSTC.

CLOCK_MCHP_MCLKPERIPH_ID_RTC

#define CLOCK_MCHP_MCLKPERIPH_ID_RTC   MCHP_CLOCK_DERIVE_ID(9, 0, 12, 0x3f, 10)

MCLK Peripheral ID: RTC.

CLOCK_MCHP_MCLKPERIPH_ID_SERCOM0

#define CLOCK_MCHP_MCLKPERIPH_ID_SERCOM0   MCHP_CLOCK_DERIVE_ID(9, 1, 4, 0x3f, 29)

MCLK Peripheral ID: SERCOM0.

CLOCK_MCHP_MCLKPERIPH_ID_SERCOM1

#define CLOCK_MCHP_MCLKPERIPH_ID_SERCOM1   MCHP_CLOCK_DERIVE_ID(9, 1, 5, 0x3f, 30)

MCLK Peripheral ID: SERCOM1.

CLOCK_MCHP_MCLKPERIPH_ID_SERCOM2

#define CLOCK_MCHP_MCLKPERIPH_ID_SERCOM2   MCHP_CLOCK_DERIVE_ID(9, 1, 6, 0x3f, 31)

MCLK Peripheral ID: SERCOM2.

CLOCK_MCHP_MCLKPERIPH_ID_SERCOM3

#define CLOCK_MCHP_MCLKPERIPH_ID_SERCOM3   MCHP_CLOCK_DERIVE_ID(9, 1, 7, 0x3f, 32)

MCLK Peripheral ID: SERCOM3.

CLOCK_MCHP_MCLKPERIPH_ID_SERCOM4

#define CLOCK_MCHP_MCLKPERIPH_ID_SERCOM4   MCHP_CLOCK_DERIVE_ID(9, 1, 12, 0x3f, 37)

MCLK Peripheral ID: SERCOM4.

CLOCK_MCHP_MCLKPERIPH_ID_SERCOM5

#define CLOCK_MCHP_MCLKPERIPH_ID_SERCOM5   MCHP_CLOCK_DERIVE_ID(9, 1, 13, 0x3f, 38)

MCLK Peripheral ID: SERCOM5.

CLOCK_MCHP_MCLKPERIPH_ID_SUPC

#define CLOCK_MCHP_MCLKPERIPH_ID_SUPC   MCHP_CLOCK_DERIVE_ID(9, 0, 4, 0x3f, 4)

MCLK Peripheral ID: SUPC.

CLOCK_MCHP_MCLKPERIPH_ID_TCC0

#define CLOCK_MCHP_MCLKPERIPH_ID_TCC0   MCHP_CLOCK_DERIVE_ID(9, 1, 8, 0x3f, 33)

MCLK Peripheral ID: TCC0.

CLOCK_MCHP_MCLKPERIPH_ID_TCC1

#define CLOCK_MCHP_MCLKPERIPH_ID_TCC1   MCHP_CLOCK_DERIVE_ID(9, 1, 9, 0x3f, 34)

MCLK Peripheral ID: TCC1.

CLOCK_MCHP_MCLKPERIPH_ID_TCC2

#define CLOCK_MCHP_MCLKPERIPH_ID_TCC2   MCHP_CLOCK_DERIVE_ID(9, 1, 10, 0x3f, 35)

MCLK Peripheral ID: TCC2.

CLOCK_MCHP_MCLKPERIPH_ID_TCC3

#define CLOCK_MCHP_MCLKPERIPH_ID_TCC3   MCHP_CLOCK_DERIVE_ID(9, 1, 11, 0x3f, 36)

MCLK Peripheral ID: TCC3.

CLOCK_MCHP_MCLKPERIPH_ID_TCC4

#define CLOCK_MCHP_MCLKPERIPH_ID_TCC4   MCHP_CLOCK_DERIVE_ID(9, 1, 14, 0x3f, 39)

MCLK Peripheral ID: TCC4.

CLOCK_MCHP_MCLKPERIPH_ID_TCC5

#define CLOCK_MCHP_MCLKPERIPH_ID_TCC5   MCHP_CLOCK_DERIVE_ID(9, 1, 15, 0x3f, 40)

MCLK Peripheral ID: TCC5.

CLOCK_MCHP_MCLKPERIPH_ID_TCC6

#define CLOCK_MCHP_MCLKPERIPH_ID_TCC6   MCHP_CLOCK_DERIVE_ID(9, 1, 16, 0x3f, 41)

MCLK Peripheral ID: TCC6.

CLOCK_MCHP_MCLKPERIPH_ID_TRAM

#define CLOCK_MCHP_MCLKPERIPH_ID_TRAM   MCHP_CLOCK_DERIVE_ID(9, 0, 15, 0x3f, 13)

MCLK Peripheral ID: TRAM.

CLOCK_MCHP_MCLKPERIPH_ID_USB_AHB

#define CLOCK_MCHP_MCLKPERIPH_ID_USB_AHB   MCHP_CLOCK_DERIVE_ID(9, 1, 22, 0x3f, 47)

MCLK Peripheral ID: USB_AHB.

CLOCK_MCHP_MCLKPERIPH_ID_USB_APB

#define CLOCK_MCHP_MCLKPERIPH_ID_USB_APB   MCHP_CLOCK_DERIVE_ID(9, 1, 23, 0x3f, 48)

MCLK Peripheral ID: USB_APB.

CLOCK_MCHP_MCLKPERIPH_ID_WDT

#define CLOCK_MCHP_MCLKPERIPH_ID_WDT   MCHP_CLOCK_DERIVE_ID(9, 0, 11, 0x3f, 9)

MCLK Peripheral ID: WDT.

CLOCK_MCHP_RTC_ID

#define CLOCK_MCHP_RTC_ID   MCHP_CLOCK_DERIVE_ID(4, 0x3f, 0x3f, 0x3f, 0)

Real-Time Counter (RTC) clock ID.

CLOCK_MCHP_RTC_ID_MAX

#define CLOCK_MCHP_RTC_ID_MAX   (0)

Maximum index for RTC clock IDs.

CLOCK_MCHP_XOSC32K_ID

#define CLOCK_MCHP_XOSC32K_ID   MCHP_CLOCK_DERIVE_ID(5, 0x3f, 0x3f, 0x3f, 0)

32 kHz External Oscillator (XOSC32K) clock ID.

CLOCK_MCHP_XOSC32K_ID_MAX

#define CLOCK_MCHP_XOSC32K_ID_MAX   (0)

Maximum index for XOSC32K clock IDs.

CLOCK_MCHP_XOSC_ID

#define CLOCK_MCHP_XOSC_ID   MCHP_CLOCK_DERIVE_ID(0, 0x3f, 0x3f, 0x3f, 0)

External Oscillator (XOSC) clock ID.

CLOCK_MCHP_XOSC_ID_MAX

#define CLOCK_MCHP_XOSC_ID_MAX   (0)

Maximum index for XOSC clock IDs.

MCHP_CLOCK_DERIVE_ID

#define MCHP_CLOCK_DERIVE_ID	(		type,
			mclkmaskreg,
			mclkmaskbit,
			gclkperiph,
			inst )

Value:

(((type) << 26) | ((mclkmaskreg) << 20) | ((mclkmaskbit) << 14) | ((gclkperiph) << 8) |    \
 inst)

Derive a 32-bit clock subsystem identifier.

Encodes the clock subsystem type, MCLK bus information, GCLK peripheral channel, and instance number into a single 32-bit identifier.

Bit field layout:

• 00..07 (8 bits): inst
• 08..13 (6 bits): gclkperiph (values from 0 to 47)
• 14..19 (6 bits): mclkmaskbit (values from 0 to 31)
• 20..25 (6 bits): mclkmaskreg following values MCLKMSK0 (0) MCLKMSK1 (1) MCLKMSK2 (2)
• 26..31 (6 bits): type following values SUBSYS_TYPE_XOSC (0) SUBSYS_TYPE_DFLL48M (1) SUBSYS_TYPE_DPLL (2) SUBSYS_TYPE_DPLL_OUT (3) SUBSYS_TYPE_RTC (4) SUBSYS_TYPE_XOSC32K (5) SUBSYS_TYPE_GCLKGEN (6) SUBSYS_TYPE_GCLKPERIPH (7) SUBSYS_TYPE_MCLKDOMAIN (8) SUBSYS_TYPE_MCLKPERIPH (9)

Parameters

type	clock subsystem type
mclkmaskreg	select from the AHBx and the APBx buses
mclkmaskbit	select the module connected to AHBx or APBx bus (0 to 31)
gclkperiph	gclk peripheral channel number m in PCHTRLm (0 to 63)
inst	instance number of the specified clock type

Returns

Encoded clock subsystem identifier