mchp_xec_pcr.h File Reference

Clock IDs for the Microchip MEC SoC series. More...

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Macros
#define	MCHP_XEC_PLL_CLK32K_SRC_SIL_OSC   0U
	PLL 32KHz clock source for full on.
#define	MCHP_XEC_PLL_CLK32K_SRC_XTAL   1U
#define	MCHP_XEC_PLL_CLK32K_SRC_PIN   2U
#define	MCHP_XEC_PERIPH_CLK32K_SRC_SO_SO   0U
	Peripheral 32KHz clock source for full on and VBAT operation.
#define	MCHP_XEC_PERIPH_CLK32K_SRC_XTAL_XTAL   1U
#define	MCHP_XEC_PERIPH_CLK32K_SRC_PIN_SO   2U
#define	MCHP_XEC_PERIPH_CLK32K_SRC_PIN_XTAL   3U
#define	MCHP_XEC_PCR_CLK_CORE   0
	clock IDs for clock control driver
#define	MCHP_XEC_PCR_CLK_CPU   1
	CPU clock.
#define	MCHP_XEC_PCR_CLK_BUS   2
	AHB clock.
#define	MCHP_XEC_PCR_CLK_PERIPH   3
	Clock for normal peripherals.
#define	MCHP_XEC_PCR_CLK_PERIPH_FAST   4
	Clock for fast peripherals.
#define	MCHP_XEC_PCR_CLK_PERIPH_SLOW   5
	Peripheral slow clock.
#define	MCHP_XEC_PCR_CLK_XTAL   6
	Clock derived from external crystal.
#define	MCHP_XEC_PCR_CLK_I3C   7
	I3C controllers input clock for SoC with I3C.
#define	MCHP_XEC_SCR_ENCODE(idx, bitpos)
	Encode a peripheral's sleep-en/clock-req/reset-en index and bit position.

Detailed Description

Clock IDs for the Microchip MEC SoC series.

Macro Definition Documentation

MCHP_XEC_PCR_CLK_BUS

#define MCHP_XEC_PCR_CLK_BUS   2

AHB clock.

MCHP_XEC_PCR_CLK_CORE

#define MCHP_XEC_PCR_CLK_CORE   0

clock IDs for clock control driver

Core clock

MCHP_XEC_PCR_CLK_CPU

#define MCHP_XEC_PCR_CLK_CPU   1

CPU clock.

MCHP_XEC_PCR_CLK_I3C

#define MCHP_XEC_PCR_CLK_I3C   7

I3C controllers input clock for SoC with I3C.

MCHP_XEC_PCR_CLK_PERIPH

#define MCHP_XEC_PCR_CLK_PERIPH   3

Clock for normal peripherals.

MCHP_XEC_PCR_CLK_PERIPH_FAST

#define MCHP_XEC_PCR_CLK_PERIPH_FAST   4

Clock for fast peripherals.

MCHP_XEC_PCR_CLK_PERIPH_SLOW

#define MCHP_XEC_PCR_CLK_PERIPH_SLOW   5

Peripheral slow clock.

MCHP_XEC_PCR_CLK_XTAL

#define MCHP_XEC_PCR_CLK_XTAL   6

Clock derived from external crystal.

MCHP_XEC_PERIPH_CLK32K_SRC_PIN_SO

#define MCHP_XEC_PERIPH_CLK32K_SRC_PIN_SO   2U

MCHP_XEC_PERIPH_CLK32K_SRC_PIN_XTAL

#define MCHP_XEC_PERIPH_CLK32K_SRC_PIN_XTAL   3U

MCHP_XEC_PERIPH_CLK32K_SRC_SO_SO

#define MCHP_XEC_PERIPH_CLK32K_SRC_SO_SO   0U

Peripheral 32KHz clock source for full on and VBAT operation.

MCHP_XEC_PERIPH_CLK32K_SRC_XTAL_XTAL

#define MCHP_XEC_PERIPH_CLK32K_SRC_XTAL_XTAL   1U

MCHP_XEC_PLL_CLK32K_SRC_PIN

#define MCHP_XEC_PLL_CLK32K_SRC_PIN   2U

MCHP_XEC_PLL_CLK32K_SRC_SIL_OSC

#define MCHP_XEC_PLL_CLK32K_SRC_SIL_OSC   0U

PLL 32KHz clock source for full on.

MCHP_XEC_PLL_CLK32K_SRC_XTAL

#define MCHP_XEC_PLL_CLK32K_SRC_XTAL   1U

MCHP_XEC_SCR_ENCODE

#define MCHP_XEC_SCR_ENCODE	(		idx,
			bitpos )

Value:

(((idx) & 0x7) | (((bitpos) & 0x1f) << 3))

Encode a peripheral's sleep-en/clock-req/reset-en index and bit position.

Parameters

idx	zero based index of PCR SCR register. Range is 0 through 4.
bitpos	position in the 32-bit PCR SCR register