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◆ DT_MEM_ARCH_ATTR_GET
◆ DT_MEM_ARCH_ATTR_MASK
#define DT_MEM_ARCH_ATTR_MASK GENMASK(31, 20) |
◆ DT_MEM_ARCH_ATTR_SHIFT
#define DT_MEM_ARCH_ATTR_SHIFT (20) |
◆ DT_MEM_ARCH_ATTR_UNKNOWN
#define DT_MEM_ARCH_ATTR_UNKNOWN BIT(31) |
◆ DT_MEM_ATTR_GET
◆ DT_MEM_ATTR_MASK
#define DT_MEM_ATTR_MASK GENMASK(15, 0) |
◆ DT_MEM_ATTR_SHIFT
#define DT_MEM_ATTR_SHIFT (0) |
◆ DT_MEM_CACHEABLE
#define DT_MEM_CACHEABLE BIT(0) /* cacheable */ |
◆ DT_MEM_DMA
#define DT_MEM_DMA BIT(3) /* DMA-able */ |
◆ DT_MEM_NON_VOLATILE
#define DT_MEM_NON_VOLATILE BIT(1) /* non-volatile */ |
◆ DT_MEM_OOO
#define DT_MEM_OOO BIT(2) /* out-of-order */ |
◆ DT_MEM_SW_ATTR_GET
◆ DT_MEM_SW_ATTR_MASK
#define DT_MEM_SW_ATTR_MASK GENMASK(19, 16) |
◆ DT_MEM_SW_ATTR_SHIFT
#define DT_MEM_SW_ATTR_SHIFT (16) |
◆ DT_MEM_SW_ATTR_UNKNOWN
#define DT_MEM_SW_ATTR_UNKNOWN BIT(19) |
◆ DT_MEM_UNKNOWN
#define DT_MEM_UNKNOWN BIT(15) /* must be last */ |