Zephyr Project API 3.7.0
A Scalable Open Source RTOS
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mii.h
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1/*
2 * Copyright (c) 2016 Piotr Mienkowski
3 * Copyright 2022 NXP
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
12#ifndef ZEPHYR_INCLUDE_NET_MII_H_
13#define ZEPHYR_INCLUDE_NET_MII_H_
14
22/* MII management registers */
24#define MII_BMCR 0x0
26#define MII_BMSR 0x1
28#define MII_PHYID1R 0x2
30#define MII_PHYID2R 0x3
32#define MII_ANAR 0x4
34#define MII_ANLPAR 0x5
36#define MII_ANER 0x6
38#define MII_ANNPTR 0x7
40#define MII_ANLPRNPR 0x8
42#define MII_1KTCR 0x9
44#define MII_1KSTSR 0xa
46#define MII_MMD_ACR 0xd
48#define MII_MMD_AADR 0xe
50#define MII_ESTAT 0xf
51
52/* Basic Mode Control Register (BMCR) bit definitions */
54#define MII_BMCR_RESET (1 << 15)
56#define MII_BMCR_LOOPBACK (1 << 14)
58#define MII_BMCR_SPEED_LSB (1 << 13)
60#define MII_BMCR_AUTONEG_ENABLE (1 << 12)
62#define MII_BMCR_POWER_DOWN (1 << 11)
64#define MII_BMCR_ISOLATE (1 << 10)
66#define MII_BMCR_AUTONEG_RESTART (1 << 9)
68#define MII_BMCR_DUPLEX_MODE (1 << 8)
70#define MII_BMCR_SPEED_MSB (1 << 6)
72#define MII_BMCR_SPEED_MASK (1 << 6 | 1 << 13)
74#define MII_BMCR_SPEED_10 (0 << 6 | 0 << 13)
76#define MII_BMCR_SPEED_100 (0 << 6 | 1 << 13)
78#define MII_BMCR_SPEED_1000 (1 << 6 | 0 << 13)
79
80/* Basic Mode Status Register (BMSR) bit definitions */
82#define MII_BMSR_100BASE_T4 (1 << 15)
84#define MII_BMSR_100BASE_X_FULL (1 << 14)
86#define MII_BMSR_100BASE_X_HALF (1 << 13)
88#define MII_BMSR_10_FULL (1 << 12)
90#define MII_BMSR_10_HALF (1 << 11)
92#define MII_BMSR_100BASE_T2_FULL (1 << 10)
94#define MII_BMSR_100BASE_T2_HALF (1 << 9)
96#define MII_BMSR_EXTEND_STATUS (1 << 8)
98#define MII_BMSR_MF_PREAMB_SUPPR (1 << 6)
100#define MII_BMSR_AUTONEG_COMPLETE (1 << 5)
102#define MII_BMSR_REMOTE_FAULT (1 << 4)
104#define MII_BMSR_AUTONEG_ABILITY (1 << 3)
106#define MII_BMSR_LINK_STATUS (1 << 2)
108#define MII_BMSR_JABBER_DETECT (1 << 1)
110#define MII_BMSR_EXTEND_CAPAB (1 << 0)
111
112/* Auto-negotiation Advertisement Register (ANAR) bit definitions */
113/* Auto-negotiation Link Partner Ability Register (ANLPAR) bit definitions */
115#define MII_ADVERTISE_NEXT_PAGE (1 << 15)
117#define MII_ADVERTISE_LPACK (1 << 14)
119#define MII_ADVERTISE_REMOTE_FAULT (1 << 13)
121#define MII_ADVERTISE_ASYM_PAUSE (1 << 11)
123#define MII_ADVERTISE_PAUSE (1 << 10)
125#define MII_ADVERTISE_100BASE_T4 (1 << 9)
127#define MII_ADVERTISE_100_FULL (1 << 8)
129#define MII_ADVERTISE_100_HALF (1 << 7)
131#define MII_ADVERTISE_10_FULL (1 << 6)
133#define MII_ADVERTISE_10_HALF (1 << 5)
135#define MII_ADVERTISE_SEL_MASK (0x1F << 0)
137#define MII_ADVERTISE_SEL_IEEE_802_3 0x01
138
139/* 1000BASE-T Control Register bit definitions */
141#define MII_ADVERTISE_1000_FULL (1 << 9)
143#define MII_ADVERTISE_1000_HALF (1 << 8)
144
146#define MII_ADVERTISE_ALL (MII_ADVERTISE_10_HALF | MII_ADVERTISE_10_FULL |\
147 MII_ADVERTISE_100_HALF | MII_ADVERTISE_100_FULL |\
148 MII_ADVERTISE_SEL_IEEE_802_3)
149
150/* Extended Status Register bit definitions */
152#define MII_ESTAT_1000BASE_X_FULL (1 << 15)
154#define MII_ESTAT_1000BASE_X_HALF (1 << 14)
156#define MII_ESTAT_1000BASE_T_FULL (1 << 13)
158#define MII_ESTAT_1000BASE_T_HALF (1 << 12)
159
164#endif /* ZEPHYR_INCLUDE_NET_MII_H_ */