mii.h

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/*
 * Copyright (c) 2016 Piotr Mienkowski
 * Copyright 2022 NXP
 *
 * SPDX-License-Identifier: Apache-2.0
 */
 
#ifndef ZEPHYR_INCLUDE_NET_MII_H_
#define ZEPHYR_INCLUDE_NET_MII_H_
 
#include <zephyr/sys/util_macro.h>
 
/* MII management registers */
#define MII_BMCR       0x0
#define MII_BMSR       0x1
#define MII_PHYID1R    0x2
#define MII_PHYID2R    0x3
#define MII_ANAR       0x4
#define MII_ANLPAR     0x5
#define MII_ANER       0x6
#define MII_ANNPTR     0x7
#define MII_ANLPRNPR   0x8
#define MII_1KTCR      0x9
#define MII_1KSTSR     0xa
#define MII_MMD_ACR    0xd
#define MII_MMD_AADR   0xe
#define MII_ESTAT      0xf
 
/* Basic Mode Control Register (BMCR) bit definitions */
#define MII_BMCR_RESET_BIT           15
#define MII_BMCR_LOOPBACK_BIT        14
#define MII_BMCR_SPEED_LSB_BIT       13
#define MII_BMCR_AUTONEG_ENABLE_BIT  12
#define MII_BMCR_POWER_DOWN_BIT      11
#define MII_BMCR_ISOLATE_BIT         10
#define MII_BMCR_AUTONEG_RESTART_BIT 9
#define MII_BMCR_DUPLEX_MODE_BIT     8
#define MII_BMCR_SPEED_MSB_BIT       6
#define MII_BMCR_RESET               BIT(MII_BMCR_RESET_BIT)
#define MII_BMCR_LOOPBACK            BIT(MII_BMCR_LOOPBACK_BIT)
#define MII_BMCR_SPEED_LSB           BIT(MII_BMCR_SPEED_LSB_BIT)
#define MII_BMCR_AUTONEG_ENABLE      BIT(MII_BMCR_AUTONEG_ENABLE_BIT)
#define MII_BMCR_POWER_DOWN          BIT(MII_BMCR_POWER_DOWN_BIT)
#define MII_BMCR_ISOLATE             BIT(MII_BMCR_ISOLATE_BIT)
#define MII_BMCR_AUTONEG_RESTART     BIT(MII_BMCR_AUTONEG_RESTART_BIT)
#define MII_BMCR_DUPLEX_MODE         BIT(MII_BMCR_DUPLEX_MODE_BIT)
#define MII_BMCR_SPEED_MSB           BIT(MII_BMCR_SPEED_MSB_BIT)
#define MII_BMCR_SPEED_MASK          (MII_BMCR_SPEED_MSB | MII_BMCR_SPEED_LSB)
#define MII_BMCR_SPEED_10            0
#define MII_BMCR_SPEED_100           BIT(MII_BMCR_SPEED_LSB_BIT)
#define MII_BMCR_SPEED_1000          BIT(MII_BMCR_SPEED_MSB_BIT)
 
/* Basic Mode Status Register (BMSR) bit definitions */
#define MII_BMSR_100BASE_T4        BIT(15)
#define MII_BMSR_100BASE_X_FULL    BIT(14)
#define MII_BMSR_100BASE_X_HALF    BIT(13)
#define MII_BMSR_10_FULL           BIT(12)
#define MII_BMSR_10_HALF           BIT(11)
#define MII_BMSR_100BASE_T2_FULL   BIT(10)
#define MII_BMSR_100BASE_T2_HALF   BIT(9)
#define MII_BMSR_EXTEND_STATUS     BIT(8)
#define MII_BMSR_MF_PREAMB_SUPPR   BIT(6)
#define MII_BMSR_AUTONEG_COMPLETE  BIT(5)
#define MII_BMSR_REMOTE_FAULT      BIT(4)
#define MII_BMSR_AUTONEG_ABILITY   BIT(3)
#define MII_BMSR_LINK_STATUS       BIT(2)
#define MII_BMSR_JABBER_DETECT     BIT(1)
#define MII_BMSR_EXTEND_CAPAB      BIT(0)
 
/* Auto-negotiation Advertisement Register (ANAR) bit definitions */
/* Auto-negotiation Link Partner Ability Register (ANLPAR) bit definitions */
#define MII_ADVERTISE_NEXT_PAGE_BIT    15
#define MII_ADVERTISE_LPACK_BIT        14
#define MII_ADVERTISE_REMOTE_FAULT_BIT 13
#define MII_ADVERTISE_ASYM_PAUSE_BIT   11
#define MII_ADVERTISE_PAUSE_BIT        10
#define MII_ADVERTISE_100BASE_T4_BIT   9
#define MII_ADVERTISE_100_FULL_BIT     8
#define MII_ADVERTISE_100_HALF_BIT     7
#define MII_ADVERTISE_10_FULL_BIT      6
#define MII_ADVERTISE_10_HALF_BIT      5
#define MII_ADVERTISE_NEXT_PAGE        BIT(MII_ADVERTISE_NEXT_PAGE_BIT)
#define MII_ADVERTISE_LPACK            BIT(MII_ADVERTISE_LPACK_BIT)
#define MII_ADVERTISE_REMOTE_FAULT     BIT(MII_ADVERTISE_REMOTE_FAULT_BIT)
#define MII_ADVERTISE_ASYM_PAUSE       BIT(MII_ADVERTISE_ASYM_PAUSE_BIT)
#define MII_ADVERTISE_PAUSE            BIT(MII_ADVERTISE_PAUSE_BIT)
#define MII_ADVERTISE_100BASE_T4       BIT(MII_ADVERTISE_100BASE_T4_BIT)
#define MII_ADVERTISE_100_FULL         BIT(MII_ADVERTISE_100_FULL_BIT)
#define MII_ADVERTISE_100_HALF         BIT(MII_ADVERTISE_100_HALF_BIT)
#define MII_ADVERTISE_10_FULL          BIT(MII_ADVERTISE_10_FULL_BIT)
#define MII_ADVERTISE_10_HALF          BIT(MII_ADVERTISE_10_HALF_BIT)
#define MII_ADVERTISE_SEL_MASK         (0x1F << 0)
#define MII_ADVERTISE_SEL_IEEE_802_3   0x01
 
/* 1000BASE-T Control Register bit definitions */
#define MII_ADVERTISE_1000_FULL_BIT 9
#define MII_ADVERTISE_1000_HALF_BIT 8
#define MII_ADVERTISE_1000_FULL     BIT(MII_ADVERTISE_1000_FULL_BIT)
#define MII_ADVERTISE_1000_HALF     BIT(MII_ADVERTISE_1000_HALF_BIT)
 
#define MII_ADVERTISE_ALL (MII_ADVERTISE_10_HALF | MII_ADVERTISE_10_FULL |\
                           MII_ADVERTISE_100_HALF | MII_ADVERTISE_100_FULL |\
                           MII_ADVERTISE_SEL_IEEE_802_3)
 
/* Extended Status Register bit definitions */
#define MII_ESTAT_1000BASE_X_FULL  BIT(15)
#define MII_ESTAT_1000BASE_X_HALF  BIT(14)
#define MII_ESTAT_1000BASE_T_FULL  BIT(13)
#define MII_ESTAT_1000BASE_T_HALF  BIT(12)
 
/* MMD Access Control Register (MII_MMD_ACR) Register bit definitions */
#define MII_MMD_ACR_DEVAD_MASK      (0x1F << 0)
#define MII_MMD_ACR_ADDR            (0x00 << 14)
#define MII_MMD_ACR_DATA_NO_POS_INC (0x01 << 14)
#define MII_MMD_ACR_DATA_RW_POS_INC (0x10 << 14)
#define MII_MMD_ACR_DATA_W_POS_INC  (0x11 << 14)
 
#endif /* ZEPHYR_INCLUDE_NET_MII_H_ */