Zephyr Project API 3.7.0
A Scalable Open Source RTOS
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msi.h
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1/*
2 * Copyright (c) 2019 Intel Corporation
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#ifndef ZEPHYR_INCLUDE_DRIVERS_PCIE_MSI_H_
8#define ZEPHYR_INCLUDE_DRIVERS_PCIE_MSI_H_
9
17#include <zephyr/kernel.h>
18#include <zephyr/types.h>
19#include <stdbool.h>
20
22
23#ifdef __cplusplus
24extern "C" {
25#endif
26
27#ifdef CONFIG_PCIE_CONTROLLER
28struct msi_vector_generic {
29 unsigned int irq;
30 uint32_t address;
31 uint16_t eventid;
32 unsigned int priority;
33};
34
35typedef struct msi_vector_generic arch_msi_vector_t;
36
37#define PCI_DEVID(bus, dev, fn) ((((bus) & 0xff) << 8) | (((dev) & 0x1f) << 3) | ((fn) & 0x07))
38#define PCI_BDF_TO_DEVID(bdf) PCI_DEVID(PCIE_BDF_TO_BUS(bdf), \
39 PCIE_BDF_TO_DEV(bdf), \
40 PCIE_BDF_TO_FUNC(bdf))
41
42#endif
43
50
51struct msi_vector {
53 arch_msi_vector_t arch;
54#ifdef CONFIG_PCIE_MSI_X
56 bool msix;
57#endif /* CONFIG_PCIE_MSI_X */
58};
59
60typedef struct msi_vector msi_vector_t;
61
62#ifdef CONFIG_PCIE_MSI_MULTI_VECTOR
63
74extern uint8_t pcie_msi_vectors_allocate(pcie_bdf_t bdf,
75 unsigned int priority,
76 msi_vector_t *vectors,
77 uint8_t n_vector);
78
90extern bool pcie_msi_vector_connect(pcie_bdf_t bdf,
91 msi_vector_t *vector,
92 void (*routine)(const void *parameter),
93 const void *parameter,
95
96#endif /* CONFIG_PCIE_MSI_MULTI_VECTOR */
97
108extern uint32_t pcie_msi_map(unsigned int irq,
109 msi_vector_t *vector,
110 uint8_t n_vector);
111
121extern uint16_t pcie_msi_mdr(unsigned int irq,
122 msi_vector_t *vector);
123
134 msi_vector_t *vectors,
135 uint8_t n_vector,
136 unsigned int irq);
137
145
146/*
147 * The first word of the MSI capability is shared with the
148 * capability ID and list link. The high 16 bits are the MCR.
149 */
150
151#define PCIE_MSI_MCR 0U
152
153#define PCIE_MSI_MCR_EN 0x00010000U /* enable MSI */
154#define PCIE_MSI_MCR_MMC 0x000E0000U /* Multi Messages Capable mask */
155#define PCIE_MSI_MCR_MMC_SHIFT 17
156#define PCIE_MSI_MCR_MME 0x00700000U /* mask of # of enabled IRQs */
157#define PCIE_MSI_MCR_MME_SHIFT 20
158#define PCIE_MSI_MCR_64 0x00800000U /* 64-bit MSI */
159
160/*
161 * The MAP follows the MCR. If PCIE_MSI_MCR_64, then the MAP
162 * is two words long. The MDR follows immediately after the MAP.
163 */
164
165#define PCIE_MSI_MAP0 1U
166#define PCIE_MSI_MAP1_64 2U
167#define PCIE_MSI_MDR_32 2U
168#define PCIE_MSI_MDR_64 3U
169
170/*
171 * As for MSI, he first word of the MSI-X capability is shared
172 * with the capability ID and list link. The high 16 bits are the MCR.
173 */
174
175#define PCIE_MSIX_MCR 0U
176
177#define PCIE_MSIX_MCR_EN 0x80000000U /* Enable MSI-X */
178#define PCIE_MSIX_MCR_FMASK 0x40000000U /* Function Mask */
179#define PCIE_MSIX_MCR_TSIZE 0x07FF0000U /* Table size mask */
180#define PCIE_MSIX_MCR_TSIZE_SHIFT 16
181#define PCIE_MSIR_TABLE_ENTRY_SIZE 16
182
183#define PCIE_MSIX_TR 1U
184#define PCIE_MSIX_TR_BIR 0x00000007U /* Table BIR mask */
185#define PCIE_MSIX_TR_OFFSET 0xFFFFFFF8U /* Offset mask */
186
187#define PCIE_MSIX_PBA 2U
188#define PCIE_MSIX_PBA_BIR 0x00000007U /* PBA BIR mask */
189#define PCIE_MSIX_PBA_OFFSET 0xFFFFFFF8U /* Offset mask */
190
191#define PCIE_VTBL_MA 0U /* Msg Address offset */
192#define PCIE_VTBL_MUA 4U /* Msg Upper Address offset */
193#define PCIE_VTBL_MD 8U /* Msg Data offset */
194#define PCIE_VTBL_VCTRL 12U /* Vector control offset */
195
196#ifdef __cplusplus
197}
198#endif
199
204#endif /* ZEPHYR_INCLUDE_DRIVERS_PCIE_MSI_H_ */
uint32_t pcie_bdf_t
A unique PCI(e) endpoint (bus, device, function).
Definition pcie.h:37
uint32_t pcie_msi_map(unsigned int irq, msi_vector_t *vector, uint8_t n_vector)
Compute the target address for an MSI posted write.
bool pcie_msi_enable(pcie_bdf_t bdf, msi_vector_t *vectors, uint8_t n_vector, unsigned int irq)
Configure the given PCI endpoint to generate MSIs.
bool pcie_is_msi(pcie_bdf_t bdf)
Check if the given PCI endpoint supports MSI/MSI-X.
uint16_t pcie_msi_mdr(unsigned int irq, msi_vector_t *vector)
Compute the data for an MSI posted write.
Public kernel APIs.
flags
Definition parser.h:96
__UINT32_TYPE__ uint32_t
Definition stdint.h:90
__UINT8_TYPE__ uint8_t
Definition stdint.h:88
__UINT16_TYPE__ uint16_t
Definition stdint.h:89
Definition msi.h:51
pcie_bdf_t bdf
Definition msi.h:52
arch_msi_vector_t arch
Definition msi.h:53
Definition msi.h:44
uint32_t msg_addr
Definition msi.h:45
uint32_t msg_up_addr
Definition msi.h:46
uint32_t vector_ctrl
Definition msi.h:48
uint32_t msg_data
Definition msi.h:47