doxygen/html/mspi__cadence_8h_source.html

/*

 * SPDX-FileCopyrightText: 2026 Texas Instruments Incorporated

 *

 * SPDX-License-Identifier: Apache-2.0

 */


#ifndef ZEPHYR_INCLUDE_DRIVERS_MSPI_CADENCE_H_

#define ZEPHYR_INCLUDE_DRIVERS_MSPI_CADENCE_H_


#include <zephyr/sys/util_macro.h>

#include <stdint.h>


struct mspi_cadence_timing_cfg {

        uint8_t rd_delay;

};


enum mspi_cadence_timing_param {

        MSPI_CADENCE_TIMING_PARAM_RD_DELAY = BIT(0)

};


#endif /* ZEPHYR_INCLUDE_DRIVERS_MSPI_CADENCE_H_ */

mspi_cadence_timing_param
mspi_cadence_timing_param
Enum which timing parameters should be modified.
Definition mspi_cadence.h:38

MSPI_CADENCE_TIMING_PARAM_RD_DELAY
@ MSPI_CADENCE_TIMING_PARAM_RD_DELAY
Read delay timing parameter.
Definition mspi_cadence.h:40

BIT
#define BIT(n)
Unsigned integer with bit position n set (signed in assembly language).
Definition util_macro.h:44

stdint.h

uint8_t
__UINT8_TYPE__ uint8_t
Definition stdint.h:88

mspi_cadence_timing_cfg
Timing configuration for the TI K3 MSPI peripheral.
Definition mspi_cadence.h:30

mspi_cadence_timing_cfg::rd_delay
uint8_t rd_delay
Amount of read data capture cycles that are applied to internal data capture circuit.
Definition mspi_cadence.h:32

util_macro.h
Macro utilities.