mtk_mt8188_clock.h

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/*
 * Copyright (c) 2026 MediaTek Inc.
 *
 * SPDX-License-Identifier: Apache-2.0
 */
 
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_MTK_MT8188_CLOCK_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_MTK_MT8188_CLOCK_H_
 
/* INFRACFG_AO */
#define CLK_INFRA_AO_PMIC_TMR             0
#define CLK_INFRA_AO_PMIC_AP              1
#define CLK_INFRA_AO_PMIC_MD              2
#define CLK_INFRA_AO_PMIC_CONN            3
#define CLK_INFRA_AO_SEJ                  4
#define CLK_INFRA_AO_APXGPT               5
#define CLK_INFRA_AO_GCE                  6
#define CLK_INFRA_AO_GCE2                 7
#define CLK_INFRA_AO_THERM                8
#define CLK_INFRA_AO_PWM_HCLK             9
#define CLK_INFRA_AO_PWM1                 10
#define CLK_INFRA_AO_PWM2                 11
#define CLK_INFRA_AO_PWM3                 12
#define CLK_INFRA_AO_PWM4                 13
#define CLK_INFRA_AO_PWM                  14
#define CLK_INFRA_AO_UART0                15
#define CLK_INFRA_AO_UART1                16
#define CLK_INFRA_AO_UART2                17
#define CLK_INFRA_AO_UART3                18
#define CLK_INFRA_AO_UART4                19
#define CLK_INFRA_AO_GCE_26M              20
#define CLK_INFRA_AO_CQ_DMA_FPC           21
#define CLK_INFRA_AO_UART5                22
#define CLK_INFRA_AO_HDMI_26M             23
#define CLK_INFRA_AO_SPI0                 24
#define CLK_INFRA_AO_MSDC0                25
#define CLK_INFRA_AO_MSDC1                26
#define CLK_INFRA_AO_MSDC2                27
#define CLK_INFRA_AO_MSDC0_SRC            28
#define CLK_INFRA_AO_DVFSRC               29
#define CLK_INFRA_AO_TRNG                 30
#define CLK_INFRA_AO_AUXADC               31
#define CLK_INFRA_AO_CPUM                 32
#define CLK_INFRA_AO_HDMI_32K             33
#define CLK_INFRA_AO_CEC_66M_HCLK         34
#define CLK_INFRA_AO_PCIE_TL_26M          35
#define CLK_INFRA_AO_MSDC1_SRC            36
#define CLK_INFRA_AO_CEC_66M_BCLK         37
#define CLK_INFRA_AO_PCIE_TL_96M          38
#define CLK_INFRA_AO_DEVICE_APC           39
#define CLK_INFRA_AO_ECC_66M_HCLK         40
#define CLK_INFRA_AO_DEBUGSYS             41
#define CLK_INFRA_AO_AUDIO                42
#define CLK_INFRA_AO_PCIE_TL_32K          43
#define CLK_INFRA_AO_DBG_TRACE            44
#define CLK_INFRA_AO_DRAMC_F26M           45
#define CLK_INFRA_AO_IRTX                 46
#define CLK_INFRA_AO_DISP_PWM             47
#define CLK_INFRA_AO_CLDMA_BCLK           48
#define CLK_INFRA_AO_AUDIO_26M_BCLK       49
#define CLK_INFRA_AO_SPI1                 50
#define CLK_INFRA_AO_SPI2                 51
#define CLK_INFRA_AO_SPI3                 52
#define CLK_INFRA_AO_FSSPM                53
#define CLK_INFRA_AO_SSPM_BUS_HCLK        54
#define CLK_INFRA_AO_APDMA_BCLK           55
#define CLK_INFRA_AO_SPI4                 56
#define CLK_INFRA_AO_SPI5                 57
#define CLK_INFRA_AO_CQ_DMA               58
#define CLK_INFRA_AO_MSDC0_SELF           59
#define CLK_INFRA_AO_MSDC1_SELF           60
#define CLK_INFRA_AO_MSDC2_SELF           61
#define CLK_INFRA_AO_I2S_DMA              62
#define CLK_INFRA_AO_AP_MSDC0             63
#define CLK_INFRA_AO_MD_MSDC0             64
#define CLK_INFRA_AO_MSDC30_2             65
#define CLK_INFRA_AO_GCPU                 66
#define CLK_INFRA_AO_PCIE_PERI_26M        67
#define CLK_INFRA_AO_GCPU_66M_BCLK        68
#define CLK_INFRA_AO_GCPU_133M_BCLK       69
#define CLK_INFRA_AO_DISP_PWM1            70
#define CLK_INFRA_AO_FBIST2FPC            71
#define CLK_INFRA_AO_DEVICE_APC_SYNC      72
#define CLK_INFRA_AO_PCIE_P1_PERI_26M     73
#define CLK_INFRA_AO_133M_MCLK_CK         74
#define CLK_INFRA_AO_66M_MCLK_CK          75
#define CLK_INFRA_AO_PCIE_PL_P_250M_P0    76
#define CLK_INFRA_AO_RG_AES_MSDCFDE_CK_0P 77
#define CLK_INFRA_AO_NR_CLK               78
 
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_MTK_MT8188_CLOCK_H_ */