Zephyr Project API 3.7.0
A Scalable Open Source RTOS
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arch.h
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1/*
2 * Copyright (c) 2016 Intel Corporation
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
14#ifndef ZEPHYR_INCLUDE_ARCH_NIOS2_ARCH_H_
15#define ZEPHYR_INCLUDE_ARCH_NIOS2_ARCH_H_
16
17#include <system.h>
18
23#include <zephyr/devicetree.h>
26#include <zephyr/sys/sys_io.h>
28
29#define ARCH_STACK_PTR_ALIGN 4
30
31#ifndef _ASMLANGUAGE
32#include <zephyr/types.h>
33#include <zephyr/irq.h>
34#include <zephyr/sw_isr_table.h>
35
36#ifdef __cplusplus
37extern "C" {
38#endif
39
40/* There is no notion of priority with the Nios II internal interrupt
41 * controller and no flags are currently supported.
42 */
43#define ARCH_IRQ_CONNECT(irq_p, priority_p, isr_p, isr_param_p, flags_p) \
44{ \
45 Z_ISR_DECLARE(irq_p, 0, isr_p, isr_param_p); \
46}
47
48static ALWAYS_INLINE unsigned int arch_irq_lock(void)
49{
50 unsigned int key, tmp;
51
52 __asm__ volatile (
53 "rdctl %[key], status\n\t"
54 "movi %[tmp], -2\n\t"
55 "and %[tmp], %[key], %[tmp]\n\t"
56 "wrctl status, %[tmp]\n\t"
57 : [key] "=r" (key), [tmp] "=r" (tmp)
58 : : "memory");
59
60 return key;
61}
62
63static ALWAYS_INLINE void arch_irq_unlock(unsigned int key)
64{
65 /* If the CPU is built without certain features, then
66 * the only writable bit in the status register is PIE
67 * in which case we can just write the value stored in key,
68 * all the other writable bits will be the same.
69 *
70 * If not, other stuff could have changed and we need to
71 * specifically flip just that bit.
72 */
73
74#if (ALT_CPU_NUM_OF_SHADOW_REG_SETS > 0) || \
75 (defined ALT_CPU_EIC_PRESENT) || \
76 (defined ALT_CPU_MMU_PRESENT) || \
77 (defined ALT_CPU_MPU_PRESENT)
78 __asm__ volatile (
79 "andi %[key], %[key], 1\n\t"
80 "beq %[key], zero, 1f\n\t"
81 "rdctl %[key], status\n\t"
82 "ori %[key], %[key], 1\n\t"
83 "wrctl status, %[key]\n\t"
84 "1:\n\t"
85 : [key] "+r" (key)
86 : : "memory");
87#else
88 __asm__ volatile (
89 "wrctl status, %[key]"
90 : : [key] "r" (key)
91 : "memory");
92#endif
93}
94
95static ALWAYS_INLINE bool arch_irq_unlocked(unsigned int key)
96{
97 return key & 1;
98}
99
100void arch_irq_enable(unsigned int irq);
101void arch_irq_disable(unsigned int irq);
102
103FUNC_NORETURN void z_SysFatalErrorHandler(unsigned int reason,
104 const struct arch_esf *esf);
105
106FUNC_NORETURN void z_NanoFatalErrorHandler(unsigned int reason,
107 const struct arch_esf *esf);
108
135
136/* Bitfield indicating which exception cause codes report a valid
137 * badaddr register. NIOS2_EXCEPTION_TLB_MISS and NIOS2_EXCEPTION_ECC_TLB_ERR
138 * are deliberately not included here, you need to check if TLBMISC.D=1
139 */
140#define NIOS2_BADADDR_CAUSE_MASK \
141 (BIT(NIOS2_EXCEPTION_SUPERVISOR_ONLY_DATA_ADDR) | \
142 BIT(NIOS2_EXCEPTION_MISALIGNED_DATA_ADDR) | \
143 BIT(NIOS2_EXCEPTION_MISALIGNED_TARGET_PC) | \
144 BIT(NIOS2_EXCEPTION_TLB_READ_PERM_VIOLATION) | \
145 BIT(NIOS2_EXCEPTION_TLB_WRITE_PERM_VIOLATION) | \
146 BIT(NIOS2_EXCEPTION_MPU_DATA_REGION_VIOLATION) | \
147 BIT(NIOS2_EXCEPTION_ECC_DATA_ERR))
148
149
151
152static inline uint32_t arch_k_cycle_get_32(void)
153{
154 return sys_clock_cycle_get_32();
155}
156
158
159static inline uint64_t arch_k_cycle_get_64(void)
160{
161 return sys_clock_cycle_get_64();
162}
163
164static ALWAYS_INLINE void arch_nop(void)
165{
166 __asm__ volatile("nop");
167}
168
169#ifdef __cplusplus
170}
171#endif
172
173#endif /* _ASMLANGUAGE */
174
175#endif /* ZEPHYR_INCLUDE_ARCH_NIOS2_ARCH_H_ */
static ALWAYS_INLINE void arch_nop(void)
Definition arch.h:348
Per-arch thread definition.
#define arch_irq_disable(irq)
Definition irq.h:107
#define arch_irq_enable(irq)
Definition irq.h:106
#define ALWAYS_INLINE
Definition common.h:129
Devicetree main header.
Public interface for configuring interrupts.
static ALWAYS_INLINE unsigned int arch_irq_lock(void)
Definition arch.h:63
static ALWAYS_INLINE void arch_irq_unlock(unsigned int key)
Definition arch.h:74
uint64_t sys_clock_cycle_get_64(void)
uint32_t sys_clock_cycle_get_32(void)
static uint32_t arch_k_cycle_get_32(void)
Definition arch.h:99
static uint64_t arch_k_cycle_get_64(void)
Definition arch.h:106
static ALWAYS_INLINE bool arch_irq_unlocked(unsigned int key)
Definition arch.h:87
nios2_exception_cause
Definition arch.h:109
@ NIOS2_EXCEPTION_ECC_DATA_CACHE_WRITEBACK_ERR
Definition arch.h:133
@ NIOS2_EXCEPTION_UNKNOWN
Definition arch.h:110
@ NIOS2_EXCEPTION_TLB_WRITE_PERM_VIOLATION
Definition arch.h:126
@ NIOS2_EXCEPTION_ECC_TLB_ERR
Definition arch.h:129
@ NIOS2_EXCEPTION_MPU_INST_REGION_VIOLATION
Definition arch.h:127
@ NIOS2_EXCEPTION_SUPERVISOR_ONLY_DATA_ADDR
Definition arch.h:122
@ NIOS2_EXCEPTION_CPU_ONLY_RESET_REQUEST
Definition arch.h:112
@ NIOS2_EXCEPTION_TLB_MISS
Definition arch.h:123
@ NIOS2_EXCEPTION_ILLEGAL_INST
Definition arch.h:116
@ NIOS2_EXCEPTION_SUPERVISOR_ONLY_INST_ADDR
Definition arch.h:120
@ NIOS2_EXCEPTION_UNIMPLEMENTED_INST
Definition arch.h:115
@ NIOS2_EXCEPTION_MPU_DATA_REGION_VIOLATION
Definition arch.h:128
@ NIOS2_EXCEPTION_ECC_FETCH_ERR
Definition arch.h:130
@ NIOS2_EXCEPTION_MISALIGNED_TARGET_PC
Definition arch.h:118
@ NIOS2_EXCEPTION_TLB_READ_PERM_VIOLATION
Definition arch.h:125
@ NIOS2_EXCEPTION_DIVISION_ERROR
Definition arch.h:119
@ NIOS2_EXCEPTION_MISALIGNED_DATA_ADDR
Definition arch.h:117
@ NIOS2_EXCEPTION_SUPERVISOR_ONLY_INST
Definition arch.h:121
@ NIOS2_EXCEPTION_TLB_EXECUTE_PERM_VIOLATION
Definition arch.h:124
@ NIOS2_EXCEPTION_TRAP_INST
Definition arch.h:114
@ NIOS2_EXCEPTION_ECC_REGISTER_FILE_ERR
Definition arch.h:131
@ NIOS2_EXCEPTION_INTERRUPT
Definition arch.h:113
@ NIOS2_EXCEPTION_ECC_DATA_ERR
Definition arch.h:132
@ NIOS2_EXCEPTION_RESET
Definition arch.h:111
static k_spinlock_key_t key
Definition spinlock_error_case.c:15
__UINT32_TYPE__ uint32_t
Definition stdint.h:90
__UINT64_TYPE__ uint64_t
Definition stdint.h:91
Exception Stack Frame.
Definition exception.h:57
Software-managed ISR table.