Zephyr Project API
4.3.99
A Scalable Open Source RTOS
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nxp_s32k566_clock.h
Go to the documentation of this file.
1
/*
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* Copyright 2025 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_NXP_S32_S32K566_CLOCK_H_
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#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_NXP_S32_S32K566_CLOCK_H_
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#define NXP_S32_FIRC_CLK 0U
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#define NXP_S32_FIRCDIV2_CLK 1U
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#define NXP_S32_SAFE_CLK 2U
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#define NXP_S32_SIRC_CLK 3U
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#define NXP_S32_FXOSC_CLK 4U
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#define NXP_S32_SXOSC_CLK 5U
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#define NXP_S32_PLL0_CLK 25U
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#define NXP_S32_PLL0_DIV_CLK 26U
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#define NXP_S32_PLL0_DIV0_CLK 27U
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#define NXP_S32_PLL0_DIV4_CLK 28U
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#define NXP_S32_PLL0_DFS0_CLK 29U
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#define NXP_S32_PLL0_DFS1_CLK 30U
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#define NXP_S32_PLL0_DFS2_CLK 31U
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#define NXP_S32_PLL0_DFS3_CLK 32U
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#define NXP_S32_PLL1_CLK 33U
25
#define NXP_S32_PLL1_DIV_CLK 34U
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#define NXP_S32_PLL1_DIV0_CLK 35U
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#define NXP_S32_CPE_PLL_CLK 36U
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#define NXP_S32_CPE_DIV_CLK 37U
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#define NXP_S32_CPE_DIV0_CLK 38U
30
#define NXP_S32_LPE_CLK 39U
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#define NXP_S32_LPE_DIV1_CLK 40U
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#define NXP_S32_LPE_DIV2_CLK 41U
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#define NXP_S32_LPE_DIV4_CLK 42U
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#define NXP_S32_LPE_DIV8_CLK 43U
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#define NXP_S32_PLT_CLK 44U
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#define NXP_S32_PLTCORE_CLK 45U
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#define NXP_S32_PLTDIV1_CLK 46U
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#define NXP_S32_PLTDIV2_CLK 47U
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#define NXP_S32_PLTDIV4_CLK 48U
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#define NXP_S32_ACP_DMA3_H_CLK 50U
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#define NXP_S32_ACP_DMA3_IPG_CLK 51U
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#define NXP_S32_ADC0_IPG_CLK 52U
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#define NXP_S32_ADC1_IPG_CLK 53U
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#define NXP_S32_BCTU_IPG_CLK 54U
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#define NXP_S32_BCTU_IPS_CLK 55U
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#define NXP_S32_CAN_HUB_IPG_CLK 56U
47
#define NXP_S32_CAN_PE_CLK 57U
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#define NXP_S32_CLKBIST_IPG_CLK 58U
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#define NXP_S32_CRC0_IPG_CLK 59U
50
#define NXP_S32_CRC1_IPG_CLK 60U
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#define NXP_S32_CSTCU_IPG_CLK 61U
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#define NXP_S32_DIG_PHY0_CLK 62U
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#define NXP_S32_DIG_PHY1_CLK 63U
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#define NXP_S32_DIG_PHY2_CLK 64U
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#define NXP_S32_DIG_PHY3_CLK 65U
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#define NXP_S32_DMA_CH_MUX0_IPG_CLK 66U
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#define NXP_S32_DMA_CH_MUX1_IPG_CLK 67U
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#define NXP_S32_DMA4_AXI_CLK 68U
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#define NXP_S32_DMA4_IPG_S_CLK 69U
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#define NXP_S32_DFT_CLK 70U
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#define NXP_S32_DSPI_CLK 71U
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#define NXP_S32_DSPI0_IPG_CLK 72U
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#define NXP_S32_DSPI1_IPG_CLK 73U
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#define NXP_S32_EDMA_TCD_CLK 74U
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#define NXP_S32_EIM0_IPG_CLK 75U
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#define NXP_S32_EIM1_IPG_CLK 76U
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#define NXP_S32_EIM2_IPG_CLK 77U
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#define NXP_S32_EIM3_IPG_CLK 78U
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#define NXP_S32_EMIOS0_IPG_CLK 79U
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#define NXP_S32_EMIOS1_IPG_CLK 80U
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#define NXP_S32_EMIOS2_IPG_CLK 81U
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#define NXP_S32_ERM0_IPG_CLK 82U
73
#define NXP_S32_ERM1_IPG_CLK 83U
74
#define NXP_S32_ERM2_IPG_CLK 84U
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#define NXP_S32_ERM3_IPG_CLK 85U
76
#define NXP_S32_ETH_TS_CLK 86U
77
#define NXP_S32_ETH0_RX_CLK 87U
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#define NXP_S32_ETH0_TX_CLK 88U
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#define NXP_S32_ETH1_RX_CLK 89U
80
#define NXP_S32_ETH1_TX_CLK 90U
81
#define NXP_S32_ETH2_RX_CLK 91U
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#define NXP_S32_ETH2_TX_CLK 92U
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#define NXP_S32_ETH3_RX_CLK 93U
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#define NXP_S32_ETH3_TX_CLK 94U
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#define NXP_S32_ETH4_RX_CLK 95U
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#define NXP_S32_ETH4_TX_CLK 96U
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#define NXP_S32_FLEXCAN_0to7_PE_CLK 97U
88
#define NXP_S32_FLEXCAN_8to10_PE_CLK 98U
89
#define NXP_S32_FLEXCAN_11to16_PE_CLK 99U
90
#define NXP_S32_FLEXCAN0_IPG_CLK 100U
91
#define NXP_S32_FLEXCAN0_PE_NOGATE_CLK 101U
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#define NXP_S32_FLEXCAN0_TS_CLK 102U
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#define NXP_S32_FLEXCAN1_IPG_CLK 103U
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#define NXP_S32_FLEXCAN1_PE_NOGATE_CLK 104U
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#define NXP_S32_FLEXCAN1_TS_CLK 105U
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#define NXP_S32_FLEXCAN2_IPG_CLK 106U
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#define NXP_S32_FLEXCAN2_PE_NOGATE_CLK 107U
98
#define NXP_S32_FLEXCAN2_TS_CLK 108U
99
#define NXP_S32_FLEXCAN3_IPG_CLK 109U
100
#define NXP_S32_FLEXCAN3_PE_NOGATE_CLK 110U
101
#define NXP_S32_FLEXCAN3_TS_CLK 111U
102
#define NXP_S32_FLEXCAN4_IPG_CLK 112U
103
#define NXP_S32_FLEXCAN4_PE_NOGATE_CLK 113U
104
#define NXP_S32_FLEXCAN4_TS_CLK 114U
105
#define NXP_S32_FLEXCAN5_IPG_CLK 115U
106
#define NXP_S32_FLEXCAN5_PE_NOGATE_CLK 116U
107
#define NXP_S32_FLEXCAN5_TS_CLK 117U
108
#define NXP_S32_FLEXCAN6_IPG_CLK 118U
109
#define NXP_S32_FLEXCAN6_PE_NOGATE_CLK 119U
110
#define NXP_S32_FLEXCAN6_TS_CLK 120U
111
#define NXP_S32_FLEXCAN7_IPG_CLK 121U
112
#define NXP_S32_FLEXCAN7_PE_NOGATE_CLK 122U
113
#define NXP_S32_FLEXCAN7_TS_CLK 123U
114
#define NXP_S32_FLEXCAN8_IPG_CLK 124U
115
#define NXP_S32_FLEXCAN8_PE_NOGATE_CLK 125U
116
#define NXP_S32_FLEXCAN8_TS_CLK 126U
117
#define NXP_S32_FLEXCAN9_IPG_CLK 127U
118
#define NXP_S32_FLEXCAN9_PE_NOGATE_CLK 128U
119
#define NXP_S32_FLEXCAN9_TS_CLK 129U
120
#define NXP_S32_FLEXCAN10_IPG_CLK 130U
121
#define NXP_S32_FLEXCAN10_PE_NOGATE_CLK 131U
122
#define NXP_S32_FLEXCAN10_TS_CLK 132U
123
#define NXP_S32_FLEXCAN11_IPG_CLK 133U
124
#define NXP_S32_FLEXCAN11_PE_NOGATE_CLK 134U
125
#define NXP_S32_FLEXCAN11_TS_CLK 135U
126
#define NXP_S32_FLEXCAN12_IPG_CLK 136U
127
#define NXP_S32_FLEXCAN12_PE_NOGATE_CLK 137U
128
#define NXP_S32_FLEXCAN12_TS_CLK 138U
129
#define NXP_S32_FLEXCAN13_IPG_CLK 139U
130
#define NXP_S32_FLEXCAN13_PE_NOGATE_CLK 140U
131
#define NXP_S32_FLEXCAN13_TS_CLK 141U
132
#define NXP_S32_FLEXCAN14_IPG_CLK 142U
133
#define NXP_S32_FLEXCAN14_PE_NOGATE_CLK 143U
134
#define NXP_S32_FLEXCAN14_TS_CLK 144U
135
#define NXP_S32_FLEXCAN15_IPG_CLK 145U
136
#define NXP_S32_FLEXCAN15_PE_NOGATE_CLK 146U
137
#define NXP_S32_FLEXCAN15_TS_CLK 147U
138
#define NXP_S32_FLEXCAN16_IPG_CLK 148U
139
#define NXP_S32_FLEXCAN16_PE_NOGATE_CLK 149U
140
#define NXP_S32_FLEXCAN16_TS_CLK 150U
141
#define NXP_S32_FLEXIO_CLK 151U
142
#define NXP_S32_FLEXIO0_IPG_CLK 152U
143
#define NXP_S32_FLEXIO0_PE_CLK 153U
144
#define NXP_S32_FLEXIO1_IPG_CLK 154U
145
#define NXP_S32_FLEXIO1_PE_CLK 155U
146
#define NXP_S32_GPR0_IPG_CLK 156U
147
#define NXP_S32_GPR1_IPG_CLK 157U
148
#define NXP_S32_INTM_IPG_CLK 158U
149
#define NXP_S32_IPSYNC_CSSI_MC_CGM_MASTER_CLK 159U
150
#define NXP_S32_IPSYNC_CSSI_MC_CGM_SLAVE_CLK 160U
151
#define NXP_S32_IPSYNC_CVFCCU_MASTER_CLK 161U
152
#define NXP_S32_IPSYNC_CVFCCU_SLAVE_CLK 162U
153
#define NXP_S32_IPSYNC_DSPI_IPI_0_MASTER_CLK 163U
154
#define NXP_S32_IPSYNC_DSPI_IPI_1_MASTER_CLK 164U
155
#define NXP_S32_IPSYNC_LPE_D_IP_FLEXCAN3_SYN_MASTER_CLK 165U
156
#define NXP_S32_IPSYNC_LPE_D_IP_FLEXCAN3_SYN_SLAVE_CLK 166U
157
#define NXP_S32_IPSYNC_LPE_D_IP_LOGIC_UNIT_SYN_MASTER_CLK 167U
158
#define NXP_S32_IPSYNC_LPE_D_IP_LOGIC_UNIT_SYN_SLAVE_CLK 168U
159
#define NXP_S32_IPSYNC_LPE_DA_IP_TEMPSENSE_C16FFC_MASTER_CLK 169U
160
#define NXP_S32_IPSYNC_LPE_DA_IP_TEMPSENSE_C16FFC_SLAVE_CLK 170U
161
#define NXP_S32_IPSYNC_LPE_LVFCCU_MASTER_CLK 171U
162
#define NXP_S32_IPSYNC_LPE_LVFCCU_SLAVE_CLK 172U
163
#define NXP_S32_IPSYNC_LPE_MC_CGM_MASTER_CLK 173U
164
#define NXP_S32_IPSYNC_LPE_MC_CGM_SLAVE_CLK 174U
165
#define NXP_S32_IPSYNC_LPE_MC_RGM_MASTER_CLK 175U
166
#define NXP_S32_IPSYNC_LPE_MC_RGM_SLAVE_CLK 176U
167
#define NXP_S32_IPSYNC_LPE_STM_MASTER_CLK 177U
168
#define NXP_S32_IPSYNC_LPE_STM_SLAVE_CLK 178U
169
#define NXP_S32_IPSYNC_LVFCCU0_MASTER_CLK 179U
170
#define NXP_S32_IPSYNC_LVFCCU0_SLAVE_CLK 180U
171
#define NXP_S32_IPSYNC_LVFCCU1_MASTER_CLK 181U
172
#define NXP_S32_IPSYNC_LVFCCU1_SLAVE_CLK 182U
173
#define NXP_S32_IPSYNC_LVFCCU2_MASTER_CLK 183U
174
#define NXP_S32_IPSYNC_LVFCCU2_SLAVE_CLK 184U
175
#define NXP_S32_IPSYNC_MC_CGM_MASTER_CLK 185U
176
#define NXP_S32_IPSYNC_MC_CGM_SLAVE_CLK 186U
177
#define NXP_S32_IPSYNC_NETC_MC_CGM_MASTER_CLK 187U
178
#define NXP_S32_IPSYNC_NETC_MC_CGM_SLAVE_CLK 188U
179
#define NXP_S32_IPSYNC_PERI_MC_CGM_MASTER_CLK 189U
180
#define NXP_S32_IPSYNC_PERI_MC_CGM_SLAVE_CLK 190U
181
#define NXP_S32_IPSYNC_SAI0_MC_CGM_MASTER_CLK 191U
182
#define NXP_S32_IPSYNC_SAI0_MC_CGM_SLAVE_CLK 192U
183
#define NXP_S32_IPSYNC_SAI1_MC_CGM_MASTER_CLK 193U
184
#define NXP_S32_IPSYNC_SAI1_MC_CGM_SLAVE_CLK 194U
185
#define NXP_S32_IPSYNC_STM0_MASTER_CLK 195U
186
#define NXP_S32_IPSYNC_STM0_SLAVE_CLK 196U
187
#define NXP_S32_IPSYNC_STM1_MASTER_CLK 197U
188
#define NXP_S32_IPSYNC_STM1_SLAVE_CLK 198U
189
#define NXP_S32_IPSYNC_STM2_MASTER_CLK 199U
190
#define NXP_S32_IPSYNC_STM2_SLAVE_CLK 200U
191
#define NXP_S32_IPSYNC_STM3_MASTER_CLK 201U
192
#define NXP_S32_IPSYNC_STM3_SLAVE_CLK 202U
193
#define NXP_S32_IPSYNC_XSPI_MASTER_CLK 203U
194
#define NXP_S32_IPSYNC_XSPI_SLAVE_CLK 204U
195
#define NXP_S32_LCU0_IPG_CLK 205U
196
#define NXP_S32_LCU1_IPG_CLK 206U
197
#define NXP_S32_LMEM_HCLK_CLK 207U
198
#define NXP_S32_LPE_ADC_IPG_CLK 208U
199
#define NXP_S32_LPE_BCTU_IPG_CLK 209U
200
#define NXP_S32_LPE_CMU_IPG_CLK 211U
201
#define NXP_S32_LPE_CRC_IPG_CLK 212U
202
#define NXP_S32_LPE_CXPI_PE_CLK 213U
203
#define NXP_S32_LPE_CXPI0_IPG_CLK 214U
204
#define NXP_S32_LPE_CXPI0_PE_CLK 215U
205
#define NXP_S32_LPE_CXPI1_IPG_CLK 216U
206
#define NXP_S32_LPE_CXPI1_PE_CLK 217U
207
#define NXP_S32_LPE_DIV1_UNGATED_CLK 218U
208
#define NXP_S32_LPE_DIV2_UNGATED_CLK 219U
209
#define NXP_S32_LPE_DIV3_UNGATED_CLK 220U
210
#define NXP_S32_LPE_DIV4_UNGATED_CLK 221U
211
#define NXP_S32_LPE_DMA_CH_MUX_IPG_CLK 222U
212
#define NXP_S32_LPE_EIM_IPG_CLK 223U
213
#define NXP_S32_LPE_FIRC_IPG_CLK 224U
214
#define NXP_S32_LPE_FLEXCAN_MOD_CLK 225U
215
#define NXP_S32_LPE_FLEXCAN_PE_CLK 226U
216
#define NXP_S32_LPE_FTM_IPG_CLK 227U
217
#define NXP_S32_LPE_FXOSC_IPG_CLK 228U
218
#define NXP_S32_LPE_GPR0_IPG_CLK 229U
219
#define NXP_S32_LPE_GPR1_IPG_CLK 230U
220
#define NXP_S32_LPE_LCU_IPG_CLK 231U
221
#define NXP_S32_LPE_LPCMP0_IPG_CLK 232U
222
#define NXP_S32_LPE_LPCMP0_RR_CLK 233U
223
#define NXP_S32_LPE_LPCMP0_SAMPLE_GATED_CLK 234U
224
#define NXP_S32_LPE_LPCMP1_IPG_CLK 235U
225
#define NXP_S32_LPE_LPCMP1_RR_CLK 236U
226
#define NXP_S32_LPE_LPCMP1_SAMPLE_GATED_CLK 237U
227
#define NXP_S32_LPE_LPCMP2_IPG_CLK 238U
228
#define NXP_S32_LPE_LPCMP2_RR_CLK 239U
229
#define NXP_S32_LPE_LPCMP2_SAMPLE_GATED_CLK 240U
230
#define NXP_S32_LPE_LPI2C_CLK 241U
231
#define NXP_S32_LPE_LPI2C_IPG_CLK 242U
232
#define NXP_S32_LPE_LPI2C_MOD_CLK 243U
233
#define NXP_S32_LPE_LPSPI_MOD_CLK 244U
234
#define NXP_S32_LPE_LPSPI0_CLK 245U
235
#define NXP_S32_LPE_LPSPI0_IPG_CLK 246U
236
#define NXP_S32_LPE_LPSPI1_CLK 247U
237
#define NXP_S32_LPE_LPSPI1_IPG_CLK 248U
238
#define NXP_S32_LPE_LPUART_MOD_CLK 249U
239
#define NXP_S32_LPE_LPUART0_CLK 250U
240
#define NXP_S32_LPE_LPUART1_CLK 252U
241
#define NXP_S32_LPE_LPUART2_CLK 254U
242
#define NXP_S32_LPE_LSTCU_IPG_CLK 256U
243
#define NXP_S32_LPE_RTC_API_FIRC_CLK 259U
244
#define NXP_S32_LPE_RTC_API_FXOSC_CLK 260U
245
#define NXP_S32_LPE_RTC_API_IPG_CLK 261U
246
#define NXP_S32_LPE_RTC_API_SIRC_CLK 262U
247
#define NXP_S32_LPE_RTC_API_SXOSC_CLK 263U
248
#define NXP_S32_LPE_SEMA42_CLK 264U
249
#define NXP_S32_LPE_STM_CLK 265U
250
#define NXP_S32_LPE_STM_IPG_CLK 266U
251
#define NXP_S32_LPE_SWT_COUNTER_IP_CLK 267U
252
#define NXP_S32_LPE_SWT_IPG_CLK 268U
253
#define NXP_S32_LPE_SXOSC_IPG_CLK 269U
254
#define NXP_S32_LPE_TRGMUX_IPG_CLK 270U
255
#define NXP_S32_LPE_TSPC_IPG_CLK 271U
256
#define NXP_S32_LPE_TSU_NS_IPG_CLK 272U
257
#define NXP_S32_LPE_UNGATED_CLK 273U
258
#define NXP_S32_LPE_VIRT_IPG_CLK 274U
259
#define NXP_S32_LPE_WKPU_IPG_CLK 275U
260
#define NXP_S32_LPI2C0_CLK 277U
261
#define NXP_S32_LPI2C1_CLK 278U
262
#define NXP_S32_LPI2C2_CLK 279U
263
#define NXP_S32_LPI2C3_CLK 280U
264
#define NXP_S32_LPSPI0_CLK 281U
265
#define NXP_S32_LPSPI1_CLK 282U
266
#define NXP_S32_LPSPI2_CLK 283U
267
#define NXP_S32_LPSPI3_CLK 284U
268
#define NXP_S32_LPSPI4_CLK 285U
269
#define NXP_S32_LPSPI5_CLK 286U
270
#define NXP_S32_LPSPI6_CLK 287U
271
#define NXP_S32_LPSPI7_CLK 288U
272
#define NXP_S32_LPUART_MSC_CLK 289U
273
#define NXP_S32_LPUART0_CLK 291U
274
#define NXP_S32_LPUART1_CLK 293U
275
#define NXP_S32_LPUART2_CLK 295U
276
#define NXP_S32_LPUART3_CLK 297U
277
#define NXP_S32_LPUART4_CLK 299U
278
#define NXP_S32_LPUART5_CLK 301U
279
#define NXP_S32_LPUART6_CLK 303U
280
#define NXP_S32_LPUART7_CLK 305U
281
#define NXP_S32_LPUART8_CLK 307U
282
#define NXP_S32_LPUART9_CLK 309U
283
#define NXP_S32_LPUART10_CLK 311U
284
#define NXP_S32_LPUART11_CLK 313U
285
#define NXP_S32_LPUART12_CLK 315U
286
#define NXP_S32_LPUART13_CLK 317U
287
#define NXP_S32_LPUART14_CLK 319U
288
#define NXP_S32_LPUART15_CLK 321U
289
#define NXP_S32_LPUART16_CLK 323U
290
#define NXP_S32_LPUART17_CLK 325U
291
#define NXP_S32_LPUART18_CLK 327U
292
#define NXP_S32_LPUART19_CLK 329U
293
#define NXP_S32_LPUART20_CLK 331U
294
#define NXP_S32_LSTCU_ACCEL_IPG_CLK 333U
295
#define NXP_S32_LSTCU_CORE0_IPG_CLK 334U
296
#define NXP_S32_LSTCU_CORE12_IPG_CLK 335U
297
#define NXP_S32_LSTCU_CORE3_IPG_CLK 336U
298
#define NXP_S32_LSTCU_HSPI_IPG_CLK 337U
299
#define NXP_S32_LSTCU_NETC_IPG_CLK 338U
300
#define NXP_S32_LSTCU_PBRIDGE1_IPG_CLK 339U
301
#define NXP_S32_LSTCU_PBRIDGE3_IPG_CLK 340U
302
#define NXP_S32_LSTCU_PBRIDGE4_IPG_CLK 341U
303
#define NXP_S32_LSTCU_REST_IPG_CLK 342U
304
#define NXP_S32_MRAM_IPG_CLK 343U
305
#define NXP_S32_MRAMC_IPG_CLK 344U
306
#define NXP_S32_MSCM_IPG_CLK 346U
307
#define NXP_S32_MSGINTR0_APB_CLK 347U
308
#define NXP_S32_MSGINTR1_APB_CLK 348U
309
#define NXP_S32_MSGINTR2_APB_CLK 349U
310
#define NXP_S32_MSGINTR3_APB_CLK 350U
311
#define NXP_S32_MSGINTR4_APB_CLK 351U
312
#define NXP_S32_MSGINTR5_APB_CLK 352U
313
#define NXP_S32_MSGINTR6_APB_CLK 353U
314
#define NXP_S32_MSGINTR7_APB_CLK 354U
315
#define NXP_S32_PERI_HIGH_SPEED_REST_USDHC_CLK 355U
316
#define NXP_S32_PERI_HIGH_SPEED_REST_XSPI_CLK 356U
317
#define NXP_S32_PERI_HIGH_SPEED_TRACE_CLK 357U
318
#define NXP_S32_PHY_ETH_CLK 358U
319
#define NXP_S32_POST_IPG_CLK 367U
320
#define NXP_S32_RR_RTC_CLK 368U
321
#define NXP_S32_RXLUT_ERM_CLK 369U
322
#define NXP_S32_RXLUT_IPG_CLK 370U
323
#define NXP_S32_SAI0_IPG_CLK 373U
324
#define NXP_S32_SAI1_IPG_CLK 375U
325
#define NXP_S32_SDHC_IPG_CLK 377U
326
#define NXP_S32_SDHC_PER_CLK 378U
327
#define NXP_S32_SEMA42_IPG_CLK 379U
328
#define NXP_S32_SERDES_ALT_REF_CLK 380U
329
#define NXP_S32_SERDES_AUX_CLK 381U
330
#define NXP_S32_SERDES_REF_CLK 382U
331
#define NXP_S32_SINC_IPG_CLK 383U
332
#define NXP_S32_SOG_REST_CMU_IPG_CLK 384U
333
#define NXP_S32_SRC_FIRC_CLK 385U
334
#define NXP_S32_SRC_FIRCDIV2_CLK 386U
335
#define NXP_S32_SRC_FXOSC_CLK 387U
336
#define NXP_S32_SRC_LPE_CLK 388U
337
#define NXP_S32_SRC_LPE_DIV1_CLK 389U
338
#define NXP_S32_SRC_LPE_DIV2_CLK 390U
339
#define NXP_S32_SRC_LPE_DIV4_CLK 391U
340
#define NXP_S32_SRC_LPE_DIV8_CLK 392U
341
#define NXP_S32_SRC_PLT_CLK 393U
342
#define NXP_S32_SRC_PLTCORE_CLK 394U
343
#define NXP_S32_SRC_PLTDIV1_CLK 395U
344
#define NXP_S32_SRC_PLTDIV2_CLK 396U
345
#define NXP_S32_SRC_PLTDIV4_CLK 397U
346
#define NXP_S32_SRC_SIRC_CLK 398U
347
#define NXP_S32_SRC_SXOSC_CLK 399U
348
#define NXP_S32_SRAM0_CONTROLLER_IPS_CLK 400U
349
#define NXP_S32_SRAM1_CONTROLLER_IPS_CLK 401U
350
#define NXP_S32_SRAM2_CONTROLLER_IPS_CLK 402U
351
#define NXP_S32_STAM_CLK 403U
352
#define NXP_S32_STM0_CLK 404U
353
#define NXP_S32_STM0_IPG_CLK 405U
354
#define NXP_S32_STM1_CLK 406U
355
#define NXP_S32_STM1_IPG_CLK 407U
356
#define NXP_S32_STM2_CLK 408U
357
#define NXP_S32_STM2_IPG_CLK 409U
358
#define NXP_S32_STM3_CLK 410U
359
#define NXP_S32_STM3_IPG_CLK 411U
360
#define NXP_S32_SWT_STARTUP_IPG_CLK 412U
361
#define NXP_S32_SWT_STARTUP_IPG_COUNTER_CLK 413U
362
#define NXP_S32_SWT0_IPG_CLK 414U
363
#define NXP_S32_SWT0_IPG_COUNTER_CLK 415U
364
#define NXP_S32_SWT1_IPG_CLK 416U
365
#define NXP_S32_SWT1_IPG_COUNTER_CLK 417U
366
#define NXP_S32_SWT2_IPG_CLK 418U
367
#define NXP_S32_SWT2_IPG_COUNTER_CLK 419U
368
#define NXP_S32_SWT3_IPG_CLK 420U
369
#define NXP_S32_SWT3_IPG_COUNTER_CLK 421U
370
#define NXP_S32_TRACE_CLK 422U
371
#define NXP_S32_VWRAP0_IPG_CLK 425U
372
#define NXP_S32_VWRAP1_IPG_CLK 426U
373
#define NXP_S32_VWRAP2_IPG_CLK 427U
374
#define NXP_S32_VWRAP3_IPG_CLK 428U
375
#define NXP_S32_XSPI_IPG_CLK 429U
376
#define NXP_S32_XSPI_UNGATED_2XSFIF_CLK 430U
377
378
#endif
/* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_NXP_S32_S32K566_CLOCK_H_ */
include
zephyr
dt-bindings
clock
nxp_s32k566_clock.h
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