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Zephyr Project API 4.3.99
A Scalable Open Source RTOS
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Zephyr Project API 4.3.99
A Scalable Open Source RTOS
|
Go to the source code of this file.
| #define NXP_S32_ACP_DMA3_H_CLK 50U |
| #define NXP_S32_ACP_DMA3_IPG_CLK 51U |
| #define NXP_S32_ADC0_IPG_CLK 52U |
| #define NXP_S32_ADC1_IPG_CLK 53U |
| #define NXP_S32_BCTU_IPG_CLK 54U |
| #define NXP_S32_BCTU_IPS_CLK 55U |
| #define NXP_S32_CAN_HUB_IPG_CLK 56U |
| #define NXP_S32_CAN_PE_CLK 57U |
| #define NXP_S32_CLKBIST_IPG_CLK 58U |
| #define NXP_S32_CPE_DIV0_CLK 38U |
| #define NXP_S32_CPE_DIV_CLK 37U |
| #define NXP_S32_CPE_PLL_CLK 36U |
| #define NXP_S32_CRC0_IPG_CLK 59U |
| #define NXP_S32_CRC1_IPG_CLK 60U |
| #define NXP_S32_CSTCU_IPG_CLK 61U |
| #define NXP_S32_DFT_CLK 70U |
| #define NXP_S32_DIG_PHY0_CLK 62U |
| #define NXP_S32_DIG_PHY1_CLK 63U |
| #define NXP_S32_DIG_PHY2_CLK 64U |
| #define NXP_S32_DIG_PHY3_CLK 65U |
| #define NXP_S32_DMA4_AXI_CLK 68U |
| #define NXP_S32_DMA4_IPG_S_CLK 69U |
| #define NXP_S32_DMA_CH_MUX0_IPG_CLK 66U |
| #define NXP_S32_DMA_CH_MUX1_IPG_CLK 67U |
| #define NXP_S32_DSPI0_IPG_CLK 72U |
| #define NXP_S32_DSPI1_IPG_CLK 73U |
| #define NXP_S32_DSPI_CLK 71U |
| #define NXP_S32_EDMA_TCD_CLK 74U |
| #define NXP_S32_EIM0_IPG_CLK 75U |
| #define NXP_S32_EIM1_IPG_CLK 76U |
| #define NXP_S32_EIM2_IPG_CLK 77U |
| #define NXP_S32_EIM3_IPG_CLK 78U |
| #define NXP_S32_EMIOS0_IPG_CLK 79U |
| #define NXP_S32_EMIOS1_IPG_CLK 80U |
| #define NXP_S32_EMIOS2_IPG_CLK 81U |
| #define NXP_S32_ERM0_IPG_CLK 82U |
| #define NXP_S32_ERM1_IPG_CLK 83U |
| #define NXP_S32_ERM2_IPG_CLK 84U |
| #define NXP_S32_ERM3_IPG_CLK 85U |
| #define NXP_S32_ETH0_RX_CLK 87U |
| #define NXP_S32_ETH0_TX_CLK 88U |
| #define NXP_S32_ETH1_RX_CLK 89U |
| #define NXP_S32_ETH1_TX_CLK 90U |
| #define NXP_S32_ETH2_RX_CLK 91U |
| #define NXP_S32_ETH2_TX_CLK 92U |
| #define NXP_S32_ETH3_RX_CLK 93U |
| #define NXP_S32_ETH3_TX_CLK 94U |
| #define NXP_S32_ETH4_RX_CLK 95U |
| #define NXP_S32_ETH4_TX_CLK 96U |
| #define NXP_S32_ETH_TS_CLK 86U |
| #define NXP_S32_FIRC_CLK 0U |
| #define NXP_S32_FIRCDIV2_CLK 1U |
| #define NXP_S32_FLEXCAN0_IPG_CLK 100U |
| #define NXP_S32_FLEXCAN0_PE_NOGATE_CLK 101U |
| #define NXP_S32_FLEXCAN0_TS_CLK 102U |
| #define NXP_S32_FLEXCAN10_IPG_CLK 130U |
| #define NXP_S32_FLEXCAN10_PE_NOGATE_CLK 131U |
| #define NXP_S32_FLEXCAN10_TS_CLK 132U |
| #define NXP_S32_FLEXCAN11_IPG_CLK 133U |
| #define NXP_S32_FLEXCAN11_PE_NOGATE_CLK 134U |
| #define NXP_S32_FLEXCAN11_TS_CLK 135U |
| #define NXP_S32_FLEXCAN12_IPG_CLK 136U |
| #define NXP_S32_FLEXCAN12_PE_NOGATE_CLK 137U |
| #define NXP_S32_FLEXCAN12_TS_CLK 138U |
| #define NXP_S32_FLEXCAN13_IPG_CLK 139U |
| #define NXP_S32_FLEXCAN13_PE_NOGATE_CLK 140U |
| #define NXP_S32_FLEXCAN13_TS_CLK 141U |
| #define NXP_S32_FLEXCAN14_IPG_CLK 142U |
| #define NXP_S32_FLEXCAN14_PE_NOGATE_CLK 143U |
| #define NXP_S32_FLEXCAN14_TS_CLK 144U |
| #define NXP_S32_FLEXCAN15_IPG_CLK 145U |
| #define NXP_S32_FLEXCAN15_PE_NOGATE_CLK 146U |
| #define NXP_S32_FLEXCAN15_TS_CLK 147U |
| #define NXP_S32_FLEXCAN16_IPG_CLK 148U |
| #define NXP_S32_FLEXCAN16_PE_NOGATE_CLK 149U |
| #define NXP_S32_FLEXCAN16_TS_CLK 150U |
| #define NXP_S32_FLEXCAN1_IPG_CLK 103U |
| #define NXP_S32_FLEXCAN1_PE_NOGATE_CLK 104U |
| #define NXP_S32_FLEXCAN1_TS_CLK 105U |
| #define NXP_S32_FLEXCAN2_IPG_CLK 106U |
| #define NXP_S32_FLEXCAN2_PE_NOGATE_CLK 107U |
| #define NXP_S32_FLEXCAN2_TS_CLK 108U |
| #define NXP_S32_FLEXCAN3_IPG_CLK 109U |
| #define NXP_S32_FLEXCAN3_PE_NOGATE_CLK 110U |
| #define NXP_S32_FLEXCAN3_TS_CLK 111U |
| #define NXP_S32_FLEXCAN4_IPG_CLK 112U |
| #define NXP_S32_FLEXCAN4_PE_NOGATE_CLK 113U |
| #define NXP_S32_FLEXCAN4_TS_CLK 114U |
| #define NXP_S32_FLEXCAN5_IPG_CLK 115U |
| #define NXP_S32_FLEXCAN5_PE_NOGATE_CLK 116U |
| #define NXP_S32_FLEXCAN5_TS_CLK 117U |
| #define NXP_S32_FLEXCAN6_IPG_CLK 118U |
| #define NXP_S32_FLEXCAN6_PE_NOGATE_CLK 119U |
| #define NXP_S32_FLEXCAN6_TS_CLK 120U |
| #define NXP_S32_FLEXCAN7_IPG_CLK 121U |
| #define NXP_S32_FLEXCAN7_PE_NOGATE_CLK 122U |
| #define NXP_S32_FLEXCAN7_TS_CLK 123U |
| #define NXP_S32_FLEXCAN8_IPG_CLK 124U |
| #define NXP_S32_FLEXCAN8_PE_NOGATE_CLK 125U |
| #define NXP_S32_FLEXCAN8_TS_CLK 126U |
| #define NXP_S32_FLEXCAN9_IPG_CLK 127U |
| #define NXP_S32_FLEXCAN9_PE_NOGATE_CLK 128U |
| #define NXP_S32_FLEXCAN9_TS_CLK 129U |
| #define NXP_S32_FLEXCAN_0to7_PE_CLK 97U |
| #define NXP_S32_FLEXCAN_11to16_PE_CLK 99U |
| #define NXP_S32_FLEXCAN_8to10_PE_CLK 98U |
| #define NXP_S32_FLEXIO0_IPG_CLK 152U |
| #define NXP_S32_FLEXIO0_PE_CLK 153U |
| #define NXP_S32_FLEXIO1_IPG_CLK 154U |
| #define NXP_S32_FLEXIO1_PE_CLK 155U |
| #define NXP_S32_FLEXIO_CLK 151U |
| #define NXP_S32_FXOSC_CLK 4U |
| #define NXP_S32_GPR0_IPG_CLK 156U |
| #define NXP_S32_GPR1_IPG_CLK 157U |
| #define NXP_S32_INTM_IPG_CLK 158U |
| #define NXP_S32_IPSYNC_CSSI_MC_CGM_MASTER_CLK 159U |
| #define NXP_S32_IPSYNC_CSSI_MC_CGM_SLAVE_CLK 160U |
| #define NXP_S32_IPSYNC_CVFCCU_MASTER_CLK 161U |
| #define NXP_S32_IPSYNC_CVFCCU_SLAVE_CLK 162U |
| #define NXP_S32_IPSYNC_DSPI_IPI_0_MASTER_CLK 163U |
| #define NXP_S32_IPSYNC_DSPI_IPI_1_MASTER_CLK 164U |
| #define NXP_S32_IPSYNC_LPE_D_IP_FLEXCAN3_SYN_MASTER_CLK 165U |
| #define NXP_S32_IPSYNC_LPE_D_IP_FLEXCAN3_SYN_SLAVE_CLK 166U |
| #define NXP_S32_IPSYNC_LPE_D_IP_LOGIC_UNIT_SYN_MASTER_CLK 167U |
| #define NXP_S32_IPSYNC_LPE_D_IP_LOGIC_UNIT_SYN_SLAVE_CLK 168U |
| #define NXP_S32_IPSYNC_LPE_DA_IP_TEMPSENSE_C16FFC_MASTER_CLK 169U |
| #define NXP_S32_IPSYNC_LPE_DA_IP_TEMPSENSE_C16FFC_SLAVE_CLK 170U |
| #define NXP_S32_IPSYNC_LPE_LVFCCU_MASTER_CLK 171U |
| #define NXP_S32_IPSYNC_LPE_LVFCCU_SLAVE_CLK 172U |
| #define NXP_S32_IPSYNC_LPE_MC_CGM_MASTER_CLK 173U |
| #define NXP_S32_IPSYNC_LPE_MC_CGM_SLAVE_CLK 174U |
| #define NXP_S32_IPSYNC_LPE_MC_RGM_MASTER_CLK 175U |
| #define NXP_S32_IPSYNC_LPE_MC_RGM_SLAVE_CLK 176U |
| #define NXP_S32_IPSYNC_LPE_STM_MASTER_CLK 177U |
| #define NXP_S32_IPSYNC_LPE_STM_SLAVE_CLK 178U |
| #define NXP_S32_IPSYNC_LVFCCU0_MASTER_CLK 179U |
| #define NXP_S32_IPSYNC_LVFCCU0_SLAVE_CLK 180U |
| #define NXP_S32_IPSYNC_LVFCCU1_MASTER_CLK 181U |
| #define NXP_S32_IPSYNC_LVFCCU1_SLAVE_CLK 182U |
| #define NXP_S32_IPSYNC_LVFCCU2_MASTER_CLK 183U |
| #define NXP_S32_IPSYNC_LVFCCU2_SLAVE_CLK 184U |
| #define NXP_S32_IPSYNC_MC_CGM_MASTER_CLK 185U |
| #define NXP_S32_IPSYNC_MC_CGM_SLAVE_CLK 186U |
| #define NXP_S32_IPSYNC_NETC_MC_CGM_MASTER_CLK 187U |
| #define NXP_S32_IPSYNC_NETC_MC_CGM_SLAVE_CLK 188U |
| #define NXP_S32_IPSYNC_PERI_MC_CGM_MASTER_CLK 189U |
| #define NXP_S32_IPSYNC_PERI_MC_CGM_SLAVE_CLK 190U |
| #define NXP_S32_IPSYNC_SAI0_MC_CGM_MASTER_CLK 191U |
| #define NXP_S32_IPSYNC_SAI0_MC_CGM_SLAVE_CLK 192U |
| #define NXP_S32_IPSYNC_SAI1_MC_CGM_MASTER_CLK 193U |
| #define NXP_S32_IPSYNC_SAI1_MC_CGM_SLAVE_CLK 194U |
| #define NXP_S32_IPSYNC_STM0_MASTER_CLK 195U |
| #define NXP_S32_IPSYNC_STM0_SLAVE_CLK 196U |
| #define NXP_S32_IPSYNC_STM1_MASTER_CLK 197U |
| #define NXP_S32_IPSYNC_STM1_SLAVE_CLK 198U |
| #define NXP_S32_IPSYNC_STM2_MASTER_CLK 199U |
| #define NXP_S32_IPSYNC_STM2_SLAVE_CLK 200U |
| #define NXP_S32_IPSYNC_STM3_MASTER_CLK 201U |
| #define NXP_S32_IPSYNC_STM3_SLAVE_CLK 202U |
| #define NXP_S32_IPSYNC_XSPI_MASTER_CLK 203U |
| #define NXP_S32_IPSYNC_XSPI_SLAVE_CLK 204U |
| #define NXP_S32_LCU0_IPG_CLK 205U |
| #define NXP_S32_LCU1_IPG_CLK 206U |
| #define NXP_S32_LMEM_HCLK_CLK 207U |
| #define NXP_S32_LPE_ADC_IPG_CLK 208U |
| #define NXP_S32_LPE_BCTU_IPG_CLK 209U |
| #define NXP_S32_LPE_CLK 39U |
| #define NXP_S32_LPE_CMU_IPG_CLK 211U |
| #define NXP_S32_LPE_CRC_IPG_CLK 212U |
| #define NXP_S32_LPE_CXPI0_IPG_CLK 214U |
| #define NXP_S32_LPE_CXPI0_PE_CLK 215U |
| #define NXP_S32_LPE_CXPI1_IPG_CLK 216U |
| #define NXP_S32_LPE_CXPI1_PE_CLK 217U |
| #define NXP_S32_LPE_CXPI_PE_CLK 213U |
| #define NXP_S32_LPE_DIV1_CLK 40U |
| #define NXP_S32_LPE_DIV1_UNGATED_CLK 218U |
| #define NXP_S32_LPE_DIV2_CLK 41U |
| #define NXP_S32_LPE_DIV2_UNGATED_CLK 219U |
| #define NXP_S32_LPE_DIV3_UNGATED_CLK 220U |
| #define NXP_S32_LPE_DIV4_CLK 42U |
| #define NXP_S32_LPE_DIV4_UNGATED_CLK 221U |
| #define NXP_S32_LPE_DIV8_CLK 43U |
| #define NXP_S32_LPE_DMA_CH_MUX_IPG_CLK 222U |
| #define NXP_S32_LPE_EIM_IPG_CLK 223U |
| #define NXP_S32_LPE_FIRC_IPG_CLK 224U |
| #define NXP_S32_LPE_FLEXCAN_MOD_CLK 225U |
| #define NXP_S32_LPE_FLEXCAN_PE_CLK 226U |
| #define NXP_S32_LPE_FTM_IPG_CLK 227U |
| #define NXP_S32_LPE_FXOSC_IPG_CLK 228U |
| #define NXP_S32_LPE_GPR0_IPG_CLK 229U |
| #define NXP_S32_LPE_GPR1_IPG_CLK 230U |
| #define NXP_S32_LPE_LCU_IPG_CLK 231U |
| #define NXP_S32_LPE_LPCMP0_IPG_CLK 232U |
| #define NXP_S32_LPE_LPCMP0_RR_CLK 233U |
| #define NXP_S32_LPE_LPCMP0_SAMPLE_GATED_CLK 234U |
| #define NXP_S32_LPE_LPCMP1_IPG_CLK 235U |
| #define NXP_S32_LPE_LPCMP1_RR_CLK 236U |
| #define NXP_S32_LPE_LPCMP1_SAMPLE_GATED_CLK 237U |
| #define NXP_S32_LPE_LPCMP2_IPG_CLK 238U |
| #define NXP_S32_LPE_LPCMP2_RR_CLK 239U |
| #define NXP_S32_LPE_LPCMP2_SAMPLE_GATED_CLK 240U |
| #define NXP_S32_LPE_LPI2C_CLK 241U |
| #define NXP_S32_LPE_LPI2C_IPG_CLK 242U |
| #define NXP_S32_LPE_LPI2C_MOD_CLK 243U |
| #define NXP_S32_LPE_LPSPI0_CLK 245U |
| #define NXP_S32_LPE_LPSPI0_IPG_CLK 246U |
| #define NXP_S32_LPE_LPSPI1_CLK 247U |
| #define NXP_S32_LPE_LPSPI1_IPG_CLK 248U |
| #define NXP_S32_LPE_LPSPI_MOD_CLK 244U |
| #define NXP_S32_LPE_LPUART0_CLK 250U |
| #define NXP_S32_LPE_LPUART1_CLK 252U |
| #define NXP_S32_LPE_LPUART2_CLK 254U |
| #define NXP_S32_LPE_LPUART_MOD_CLK 249U |
| #define NXP_S32_LPE_LSTCU_IPG_CLK 256U |
| #define NXP_S32_LPE_RTC_API_FIRC_CLK 259U |
| #define NXP_S32_LPE_RTC_API_FXOSC_CLK 260U |
| #define NXP_S32_LPE_RTC_API_IPG_CLK 261U |
| #define NXP_S32_LPE_RTC_API_SIRC_CLK 262U |
| #define NXP_S32_LPE_RTC_API_SXOSC_CLK 263U |
| #define NXP_S32_LPE_SEMA42_CLK 264U |
| #define NXP_S32_LPE_STM_CLK 265U |
| #define NXP_S32_LPE_STM_IPG_CLK 266U |
| #define NXP_S32_LPE_SWT_COUNTER_IP_CLK 267U |
| #define NXP_S32_LPE_SWT_IPG_CLK 268U |
| #define NXP_S32_LPE_SXOSC_IPG_CLK 269U |
| #define NXP_S32_LPE_TRGMUX_IPG_CLK 270U |
| #define NXP_S32_LPE_TSPC_IPG_CLK 271U |
| #define NXP_S32_LPE_TSU_NS_IPG_CLK 272U |
| #define NXP_S32_LPE_UNGATED_CLK 273U |
| #define NXP_S32_LPE_VIRT_IPG_CLK 274U |
| #define NXP_S32_LPE_WKPU_IPG_CLK 275U |
| #define NXP_S32_LPI2C0_CLK 277U |
| #define NXP_S32_LPI2C1_CLK 278U |
| #define NXP_S32_LPI2C2_CLK 279U |
| #define NXP_S32_LPI2C3_CLK 280U |
| #define NXP_S32_LPSPI0_CLK 281U |
| #define NXP_S32_LPSPI1_CLK 282U |
| #define NXP_S32_LPSPI2_CLK 283U |
| #define NXP_S32_LPSPI3_CLK 284U |
| #define NXP_S32_LPSPI4_CLK 285U |
| #define NXP_S32_LPSPI5_CLK 286U |
| #define NXP_S32_LPSPI6_CLK 287U |
| #define NXP_S32_LPSPI7_CLK 288U |
| #define NXP_S32_LPUART0_CLK 291U |
| #define NXP_S32_LPUART10_CLK 311U |
| #define NXP_S32_LPUART11_CLK 313U |
| #define NXP_S32_LPUART12_CLK 315U |
| #define NXP_S32_LPUART13_CLK 317U |
| #define NXP_S32_LPUART14_CLK 319U |
| #define NXP_S32_LPUART15_CLK 321U |
| #define NXP_S32_LPUART16_CLK 323U |
| #define NXP_S32_LPUART17_CLK 325U |
| #define NXP_S32_LPUART18_CLK 327U |
| #define NXP_S32_LPUART19_CLK 329U |
| #define NXP_S32_LPUART1_CLK 293U |
| #define NXP_S32_LPUART20_CLK 331U |
| #define NXP_S32_LPUART2_CLK 295U |
| #define NXP_S32_LPUART3_CLK 297U |
| #define NXP_S32_LPUART4_CLK 299U |
| #define NXP_S32_LPUART5_CLK 301U |
| #define NXP_S32_LPUART6_CLK 303U |
| #define NXP_S32_LPUART7_CLK 305U |
| #define NXP_S32_LPUART8_CLK 307U |
| #define NXP_S32_LPUART9_CLK 309U |
| #define NXP_S32_LPUART_MSC_CLK 289U |
| #define NXP_S32_LSTCU_ACCEL_IPG_CLK 333U |
| #define NXP_S32_LSTCU_CORE0_IPG_CLK 334U |
| #define NXP_S32_LSTCU_CORE12_IPG_CLK 335U |
| #define NXP_S32_LSTCU_CORE3_IPG_CLK 336U |
| #define NXP_S32_LSTCU_HSPI_IPG_CLK 337U |
| #define NXP_S32_LSTCU_NETC_IPG_CLK 338U |
| #define NXP_S32_LSTCU_PBRIDGE1_IPG_CLK 339U |
| #define NXP_S32_LSTCU_PBRIDGE3_IPG_CLK 340U |
| #define NXP_S32_LSTCU_PBRIDGE4_IPG_CLK 341U |
| #define NXP_S32_LSTCU_REST_IPG_CLK 342U |
| #define NXP_S32_MRAM_IPG_CLK 343U |
| #define NXP_S32_MRAMC_IPG_CLK 344U |
| #define NXP_S32_MSCM_IPG_CLK 346U |
| #define NXP_S32_MSGINTR0_APB_CLK 347U |
| #define NXP_S32_MSGINTR1_APB_CLK 348U |
| #define NXP_S32_MSGINTR2_APB_CLK 349U |
| #define NXP_S32_MSGINTR3_APB_CLK 350U |
| #define NXP_S32_MSGINTR4_APB_CLK 351U |
| #define NXP_S32_MSGINTR5_APB_CLK 352U |
| #define NXP_S32_MSGINTR6_APB_CLK 353U |
| #define NXP_S32_MSGINTR7_APB_CLK 354U |
| #define NXP_S32_PERI_HIGH_SPEED_REST_USDHC_CLK 355U |
| #define NXP_S32_PERI_HIGH_SPEED_REST_XSPI_CLK 356U |
| #define NXP_S32_PERI_HIGH_SPEED_TRACE_CLK 357U |
| #define NXP_S32_PHY_ETH_CLK 358U |
| #define NXP_S32_PLL0_CLK 25U |
| #define NXP_S32_PLL0_DFS0_CLK 29U |
| #define NXP_S32_PLL0_DFS1_CLK 30U |
| #define NXP_S32_PLL0_DFS2_CLK 31U |
| #define NXP_S32_PLL0_DFS3_CLK 32U |
| #define NXP_S32_PLL0_DIV0_CLK 27U |
| #define NXP_S32_PLL0_DIV4_CLK 28U |
| #define NXP_S32_PLL0_DIV_CLK 26U |
| #define NXP_S32_PLL1_CLK 33U |
| #define NXP_S32_PLL1_DIV0_CLK 35U |
| #define NXP_S32_PLL1_DIV_CLK 34U |
| #define NXP_S32_PLT_CLK 44U |
| #define NXP_S32_PLTCORE_CLK 45U |
| #define NXP_S32_PLTDIV1_CLK 46U |
| #define NXP_S32_PLTDIV2_CLK 47U |
| #define NXP_S32_PLTDIV4_CLK 48U |
| #define NXP_S32_POST_IPG_CLK 367U |
| #define NXP_S32_RR_RTC_CLK 368U |
| #define NXP_S32_RXLUT_ERM_CLK 369U |
| #define NXP_S32_RXLUT_IPG_CLK 370U |
| #define NXP_S32_SAFE_CLK 2U |
| #define NXP_S32_SAI0_IPG_CLK 373U |
| #define NXP_S32_SAI1_IPG_CLK 375U |
| #define NXP_S32_SDHC_IPG_CLK 377U |
| #define NXP_S32_SDHC_PER_CLK 378U |
| #define NXP_S32_SEMA42_IPG_CLK 379U |
| #define NXP_S32_SERDES_ALT_REF_CLK 380U |
| #define NXP_S32_SERDES_AUX_CLK 381U |
| #define NXP_S32_SERDES_REF_CLK 382U |
| #define NXP_S32_SINC_IPG_CLK 383U |
| #define NXP_S32_SIRC_CLK 3U |
| #define NXP_S32_SOG_REST_CMU_IPG_CLK 384U |
| #define NXP_S32_SRAM0_CONTROLLER_IPS_CLK 400U |
| #define NXP_S32_SRAM1_CONTROLLER_IPS_CLK 401U |
| #define NXP_S32_SRAM2_CONTROLLER_IPS_CLK 402U |
| #define NXP_S32_SRC_FIRC_CLK 385U |
| #define NXP_S32_SRC_FIRCDIV2_CLK 386U |
| #define NXP_S32_SRC_FXOSC_CLK 387U |
| #define NXP_S32_SRC_LPE_CLK 388U |
| #define NXP_S32_SRC_LPE_DIV1_CLK 389U |
| #define NXP_S32_SRC_LPE_DIV2_CLK 390U |
| #define NXP_S32_SRC_LPE_DIV4_CLK 391U |
| #define NXP_S32_SRC_LPE_DIV8_CLK 392U |
| #define NXP_S32_SRC_PLT_CLK 393U |
| #define NXP_S32_SRC_PLTCORE_CLK 394U |
| #define NXP_S32_SRC_PLTDIV1_CLK 395U |
| #define NXP_S32_SRC_PLTDIV2_CLK 396U |
| #define NXP_S32_SRC_PLTDIV4_CLK 397U |
| #define NXP_S32_SRC_SIRC_CLK 398U |
| #define NXP_S32_SRC_SXOSC_CLK 399U |
| #define NXP_S32_STAM_CLK 403U |
| #define NXP_S32_STM0_CLK 404U |
| #define NXP_S32_STM0_IPG_CLK 405U |
| #define NXP_S32_STM1_CLK 406U |
| #define NXP_S32_STM1_IPG_CLK 407U |
| #define NXP_S32_STM2_CLK 408U |
| #define NXP_S32_STM2_IPG_CLK 409U |
| #define NXP_S32_STM3_CLK 410U |
| #define NXP_S32_STM3_IPG_CLK 411U |
| #define NXP_S32_SWT0_IPG_CLK 414U |
| #define NXP_S32_SWT0_IPG_COUNTER_CLK 415U |
| #define NXP_S32_SWT1_IPG_CLK 416U |
| #define NXP_S32_SWT1_IPG_COUNTER_CLK 417U |
| #define NXP_S32_SWT2_IPG_CLK 418U |
| #define NXP_S32_SWT2_IPG_COUNTER_CLK 419U |
| #define NXP_S32_SWT3_IPG_CLK 420U |
| #define NXP_S32_SWT3_IPG_COUNTER_CLK 421U |
| #define NXP_S32_SWT_STARTUP_IPG_CLK 412U |
| #define NXP_S32_SWT_STARTUP_IPG_COUNTER_CLK 413U |
| #define NXP_S32_SXOSC_CLK 5U |
| #define NXP_S32_TRACE_CLK 422U |
| #define NXP_S32_VWRAP0_IPG_CLK 425U |
| #define NXP_S32_VWRAP1_IPG_CLK 426U |
| #define NXP_S32_VWRAP2_IPG_CLK 427U |
| #define NXP_S32_VWRAP3_IPG_CLK 428U |
| #define NXP_S32_XSPI_IPG_CLK 429U |
| #define NXP_S32_XSPI_UNGATED_2XSFIF_CLK 430U |
1.14.0