Zephyr Project API 4.4.99
A Scalable Open Source RTOS
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Devicetree pin control helpers for Renesas RZ/G (RZ/G3S). More...

Go to the source code of this file.

Macros

#define RZG_PINMUX(port, pin, func)
 Create an encoded value containing port/pin/function information.
#define RZG_FILTER_SET(filnum, filclksel)
 Encode filter stage count and clock selection into one configuration value.
Renesas RZ/G digital noise filter options

Set the number of filter stages (FILNUM) and the sampling clock divider (FILCLKSEL).

#define RZG_FILNUM_4_STAGE   0
 FILNUM: 4-stage filter.
#define RZG_FILNUM_8_STAGE   1
 FILNUM: 8-stage filter.
#define RZG_FILNUM_12_STAGE   2
 FILNUM: 12-stage filter.
#define RZG_FILNUM_16_STAGE   3
 FILNUM: 16-stage filter.
#define RZG_FILCLKSEL_NOT_DIV   0
 FILCLKSEL: no division.
#define RZG_FILCLKSEL_DIV_9000   1
 FILCLKSEL: divided by 9000.
#define RZG_FILCLKSEL_DIV_18000   2
 FILCLKSEL: divided by 18000.
#define RZG_FILCLKSEL_DIV_36000   3
 FILCLKSEL: divided by 36000.

Detailed Description

Devicetree pin control helpers for Renesas RZ/G (RZ/G3S).