pmuv3.h

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/*
 * Copyright (c) 2026 Advanced Micro Devices, Inc.
 *
 * SPDX-License-Identifier: Apache-2.0
 */

 
#ifndef ZEPHYR_INCLUDE_ARCH_ARM64_PMUV3_H_
#define ZEPHYR_INCLUDE_ARCH_ARM64_PMUV3_H_
 
#include <zephyr/sys/util.h>
#include <stdint.h>
 
#ifdef __cplusplus
extern "C" {
#endif

struct pmu_info {
        uint32_t implementer;
        uint32_t idcode;
};

typedef struct pmu_info pmu_info_t;

typedef enum {
        PMU_EVT_SW_INCR = 0x00,          
        PMU_EVT_L1I_CACHE_REFILL = 0x01, 
        PMU_EVT_L1I_TLB_REFILL = 0x02,   
        PMU_EVT_L1D_CACHE_REFILL = 0x03, 
        PMU_EVT_L1D_CACHE = 0x04,        
        PMU_EVT_L1D_TLB_REFILL = 0x05,   
        PMU_EVT_INST_RETIRED = 0x08,     
        PMU_EVT_EXC_TAKEN = 0x09,        
        PMU_EVT_EXC_RETURN = 0x0A,   
        PMU_EVT_BR_MIS_PRED = 0x10,  
        PMU_EVT_CPU_CYCLES = 0x11,   
        PMU_EVT_BR_PRED = 0x12,      
        PMU_EVT_MEM_ACCESS = 0x13,   
        PMU_EVT_L1I_CACHE = 0x14,    
        PMU_EVT_L1D_CACHE_WB = 0x15, 
        PMU_EVT_L2D_CACHE = 0x16,    
        PMU_EVT_L2D_CACHE_REFILL = 0x17,   
        PMU_EVT_L2D_CACHE_WB = 0x18,       
        PMU_EVT_BUS_ACCESS = 0x19,         
        PMU_EVT_MEMORY_ERROR = 0x1A,       
        PMU_EVT_INST_SPEC = 0x1B,          
        PMU_EVT_TTBR_WRITE_RETIRED = 0x1C, 
        PMU_EVT_BUS_CYCLES = 0x1D,         
} pmu_evt_t;

#define PMCR_E  BIT(0)
#define PMCR_P  BIT(1)
#define PMCR_C  BIT(2)
#define PMCR_D  BIT(3)
#define PMCR_X  BIT(4)
#define PMCR_DP BIT(5)
#define PMCR_LC BIT(6)
#define PMCR_LP BIT(7)

#define PMCR_N_SHIFT      11
#define PMCR_N_MASK       0x1F
#define PMCR_IDCODE_SHIFT 16
#define PMCR_IDCODE_MASK  0xFF
#define PMCR_IMP_SHIFT    24
#define PMCR_IMP_MASK     0xFF

#define PMUSERENR_EN BIT(0)
#define PMUSERENR_SW BIT(1)
#define PMUSERENR_CR BIT(2)
#define PMUSERENR_ER BIT(3)

 
int arch_pmu_init(void);
uint32_t arch_pmu_num_counters(void);
void arch_pmu_get_info(pmu_info_t *info);
int arch_pmu_counter_config(uint32_t counter, pmu_evt_t event);
void arch_pmu_counter_enable(uint32_t counter);
void arch_pmu_counter_disable(uint32_t counter);
void arch_pmu_counter_enable_all(void);
void arch_pmu_counter_disable_all(void);
uint64_t arch_pmu_counter_read(uint32_t counter);
void arch_pmu_counter_reset(uint32_t counter);
void arch_pmu_counter_reset_all(void);
uint64_t arch_pmu_cycle_count(void);
void arch_pmu_cycle_reset(void);
void arch_pmu_start(void);
void arch_pmu_stop(void);
bool arch_pmu_counter_overflow(uint32_t counter);
void arch_pmu_counter_clear_overflow(uint32_t counter);
 
#define pmu_init                   arch_pmu_init
#define pmu_num_counters           arch_pmu_num_counters
#define pmu_get_info               arch_pmu_get_info
#define pmu_counter_config         arch_pmu_counter_config
#define pmu_counter_enable         arch_pmu_counter_enable
#define pmu_counter_disable        arch_pmu_counter_disable
#define pmu_counter_enable_all     arch_pmu_counter_enable_all
#define pmu_counter_disable_all    arch_pmu_counter_disable_all
#define pmu_counter_read           arch_pmu_counter_read
#define pmu_counter_reset          arch_pmu_counter_reset
#define pmu_counter_reset_all      arch_pmu_counter_reset_all
#define pmu_cycle_count            arch_pmu_cycle_count
#define pmu_cycle_reset            arch_pmu_cycle_reset
#define pmu_start                  arch_pmu_start
#define pmu_stop                   arch_pmu_stop
#define pmu_counter_overflow       arch_pmu_counter_overflow
#define pmu_counter_clear_overflow arch_pmu_counter_clear_overflow



uint32_t arch_pmu_cpu_freq_mhz(void);

const char *arch_pmu_event_name(uint32_t event);

 
#ifdef __cplusplus
}
#endif
 
#endif /* ZEPHYR_INCLUDE_ARCH_ARM64_PMUV3_H_ */