pmuv3.h File Reference

ARMv8-A AArch64 PMUv3 — architectural events and register bits. More...

#include <zephyr/sys/util.h>
#include <stdint.h>

Go to the source code of this file.

Data Structures
struct	pmu_info
	PMU identification for the current logical CPU (after pmu_init). More...

Macros
#define	PMCR_E   BIT(0)
	PMCR_EL0: enable all counters.
#define	PMCR_P   BIT(1)
	PMCR_EL0: reset all event counters.
#define	PMCR_C   BIT(2)
	PMCR_EL0: cycle counter reset.
#define	PMCR_D   BIT(3)
	PMCR_EL0: clock divider (1 = every 64 cycles).
#define	PMCR_X   BIT(4)
	PMCR_EL0: export enable.
#define	PMCR_DP   BIT(5)
	PMCR_EL0: disable cycle counter in EL2.
#define	PMCR_LC   BIT(6)
	PMCR_EL0: long cycle counter (64-bit).
#define	PMCR_LP   BIT(7)
	PMCR_EL0: long event counter enable.
#define	PMCR_N_SHIFT   11
	PMCR_EL0 bit position for event counter count field.
#define	PMCR_N_MASK   0x1F
	PMCR_EL0 mask for number of implemented event counters.
#define	PMCR_IDCODE_SHIFT   16
	PMCR_EL0 bit position for ID code field.
#define	PMCR_IDCODE_MASK   0xFF
	PMCR_EL0 mask for ID code field.
#define	PMCR_IMP_SHIFT   24
	PMCR_EL0 bit position for implementer code field.
#define	PMCR_IMP_MASK   0xFF
	PMCR_EL0 mask for implementer code field.
#define	PMUSERENR_EN   BIT(0)
	PMUSERENR_EL0: user-mode PMU access enable.
#define	PMUSERENR_SW   BIT(1)
	PMUSERENR_EL0: software increment at EL0.
#define	PMUSERENR_CR   BIT(2)
	PMUSERENR_EL0: cycle counter read at EL0.
#define	PMUSERENR_ER   BIT(3)
	PMUSERENR_EL0: event counter read at EL0.

Typedefs
typedef struct pmu_info	pmu_info_t
	Typedef for pmu_info.

Enumerations
enum	pmu_evt_t {   PMU_EVT_SW_INCR = 0x00 , PMU_EVT_L1I_CACHE_REFILL = 0x01 , PMU_EVT_L1I_TLB_REFILL = 0x02 , PMU_EVT_L1D_CACHE_REFILL = 0x03 ,   PMU_EVT_L1D_CACHE = 0x04 , PMU_EVT_L1D_TLB_REFILL = 0x05 , PMU_EVT_INST_RETIRED = 0x08 , PMU_EVT_EXC_TAKEN = 0x09 ,   PMU_EVT_EXC_RETURN = 0x0A , PMU_EVT_BR_MIS_PRED = 0x10 , PMU_EVT_CPU_CYCLES = 0x11 , PMU_EVT_BR_PRED = 0x12 ,   PMU_EVT_MEM_ACCESS = 0x13 , PMU_EVT_L1I_CACHE = 0x14 , PMU_EVT_L1D_CACHE_WB = 0x15 , PMU_EVT_L2D_CACHE = 0x16 ,   PMU_EVT_L2D_CACHE_REFILL = 0x17 , PMU_EVT_L2D_CACHE_WB = 0x18 , PMU_EVT_BUS_ACCESS = 0x19 , PMU_EVT_MEMORY_ERROR = 0x1A ,   PMU_EVT_INST_SPEC = 0x1B , PMU_EVT_TTBR_WRITE_RETIRED = 0x1C , PMU_EVT_BUS_CYCLES = 0x1D }
	Arm architectural PMU event encoding (PMUv3, 0x00–0x1F). More...

Functions
Diagnostic helpers (not portable @c pmu_*() primitives)
uint32_t	arch_pmu_cpu_freq_mhz (void)
	Calibrated CPU MHz from pmu_init (PMU cycle counter vs system timer).
const char *	arch_pmu_event_name (uint32_t event)
	Human-readable name for event, or "UNKNOWN".

Detailed Description

ARMv8-A AArch64 PMUv3 — architectural events and register bits.

Portable applications should include <zephyr/arch/pmu.h> for the pmu_*() API. This header defines pmu_info_t, pmu_evt_t (Arm architectural PMU event numbers in the 0x00-0x1F range), and PMCR_EL0 / PMUSERENR_EL0 bits.

Macro Definition Documentation

PMCR_C

#define PMCR_C   BIT(2)

PMCR_EL0: cycle counter reset.

PMCR_D

#define PMCR_D   BIT(3)

PMCR_EL0: clock divider (1 = every 64 cycles).

PMCR_DP

#define PMCR_DP   BIT(5)

PMCR_EL0: disable cycle counter in EL2.

PMCR_E

#define PMCR_E   BIT(0)

PMCR_EL0: enable all counters.

PMCR_IDCODE_MASK

#define PMCR_IDCODE_MASK   0xFF

PMCR_EL0 mask for ID code field.

PMCR_IDCODE_SHIFT

#define PMCR_IDCODE_SHIFT   16

PMCR_EL0 bit position for ID code field.

PMCR_IMP_MASK

#define PMCR_IMP_MASK   0xFF

PMCR_EL0 mask for implementer code field.

PMCR_IMP_SHIFT

#define PMCR_IMP_SHIFT   24

PMCR_EL0 bit position for implementer code field.

PMCR_LC

#define PMCR_LC   BIT(6)

PMCR_EL0: long cycle counter (64-bit).

When set, determines when unsigned overflow of the cycle counter is recorded in PMOVSCLR_EL0.C.

PMCR_LP

#define PMCR_LP   BIT(7)

PMCR_EL0: long event counter enable.

When set, determines when unsigned overflow of each event counter is recorded in PMOVSCLR_EL0.P[n].

PMCR_N_MASK

#define PMCR_N_MASK   0x1F

PMCR_EL0 mask for number of implemented event counters.

PMCR_N_SHIFT

#define PMCR_N_SHIFT   11

PMCR_EL0 bit position for event counter count field.

PMCR_P

#define PMCR_P   BIT(1)

PMCR_EL0: reset all event counters.

PMCR_X

#define PMCR_X   BIT(4)

PMCR_EL0: export enable.

PMUSERENR_CR

#define PMUSERENR_CR   BIT(2)

PMUSERENR_EL0: cycle counter read at EL0.

PMUSERENR_EN

#define PMUSERENR_EN   BIT(0)

PMUSERENR_EL0: user-mode PMU access enable.

PMUSERENR_ER

#define PMUSERENR_ER   BIT(3)

PMUSERENR_EL0: event counter read at EL0.

PMUSERENR_SW

#define PMUSERENR_SW   BIT(1)

PMUSERENR_EL0: software increment at EL0.

Typedef Documentation

pmu_info_t

typedef struct pmu_info pmu_info_t

Typedef for pmu_info.

Enumeration Type Documentation

pmu_evt_t

enum pmu_evt_t

Arm architectural PMU event encoding (PMUv3, 0x00–0x1F).

Names and values follow the Arm Architecture Reference Manual.

Enumerator
PMU_EVT_SW_INCR	Software increment.
PMU_EVT_L1I_CACHE_REFILL	L1 instruction cache refill.
PMU_EVT_L1I_TLB_REFILL	L1 instruction TLB refill.
PMU_EVT_L1D_CACHE_REFILL	L1 data cache refill.
PMU_EVT_L1D_CACHE	L1 data cache access.
PMU_EVT_L1D_TLB_REFILL	L1 data TLB refill.
PMU_EVT_INST_RETIRED	Instruction architecturally executed.
PMU_EVT_EXC_TAKEN	Exception taken.
PMU_EVT_EXC_RETURN	Instruction architecturally executed (exception return).
PMU_EVT_BR_MIS_PRED	Mispredicted or not-predicted branch.
PMU_EVT_CPU_CYCLES	Cycle.
PMU_EVT_BR_PRED	Predictable branch.
PMU_EVT_MEM_ACCESS	Data memory access.
PMU_EVT_L1I_CACHE	L1 instruction cache access.
PMU_EVT_L1D_CACHE_WB	L1 data cache write-back.
PMU_EVT_L2D_CACHE	L2 data cache access.
PMU_EVT_L2D_CACHE_REFILL	L2 data cache refill.
PMU_EVT_L2D_CACHE_WB	L2 data cache write-back.
PMU_EVT_BUS_ACCESS	Bus access.
PMU_EVT_MEMORY_ERROR	Local memory error.
PMU_EVT_INST_SPEC	Instruction speculatively executed.
PMU_EVT_TTBR_WRITE_RETIRED	Instruction architecturally executed (TTBR write).
PMU_EVT_BUS_CYCLES	Bus cycle.

Function Documentation

arch_pmu_cpu_freq_mhz()

uint32_t arch_pmu_cpu_freq_mhz

(

void

)

Calibrated CPU MHz from pmu_init (PMU cycle counter vs system timer).

arch_pmu_event_name()

const char * arch_pmu_event_name

(

uint32_t

event

)

Human-readable name for event, or "UNKNOWN".