renesas-rztn-gpio.h File Reference

Renesas RZ/T,N GPIO flags for Zephyr. More...

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Macros
Renesas RZ/T,N Region Select Options
Set the safety attribute for I/O ports (RSELP)
#define	RZTN_GPIO_SAFETY   0U
	Safety region.
#define	RZTN_GPIO_NONSAFETY   BIT(14)
	Non safety region.
#define	RZTN_GPIO_DRCTL_SET(drive_ability, schmitt_trig, slew_rate)
	Encode settings for DRCTL register into one configuration value.

Detailed Description

Renesas RZ/T,N GPIO flags for Zephyr.

The additional flags are encoded in the 8 upper bits of gpio_dt_flags_t as follows:

• bits [9:8] = Driving ability control (0=Low, 1=Middle, 2=High, 3=Ultral High)
• bits [12] = Schmitt trigger control (0=Disable, 1=Enable)
• bits [13] = Slew rate control (0=Slow, 1=Fast)
• bits [14] = Safety region (0=Safety, 1=Non safety)

Example DT usage:

• Driving ability control: Middle
• Schmitt trigger control: Enabled
• Slew rate control: Slow
• Non safety

gpio-consumer {
    out-gpios = <&port8 2 (GPIO_PULL_UP | RZTN_GPIO_CFG_SET(1, 1, 0) | RZTN_GPIO_NONSAFETY)>;
};

Macro Definition Documentation

RZTN_GPIO_DRCTL_SET

#define RZTN_GPIO_DRCTL_SET	(		drive_ability,
			schmitt_trig,
			slew_rate )

Value:

        (((drive_ability) | ((schmitt_trig) << RZTN_GPIO_SCHMITT_TRIG_SHIFT) |                     \
          ((slew_rate) << RZTN_GPIO_SLEW_RATE_SHIFT))                                              \
         << RZTN_GPIO_DRCTL_SHIFT)

Encode settings for DRCTL register into one configuration value.

Encodings:

• bits [9:8] = Driving ability control (0=Low, 1=Middle, 2=High, 3=Ultra High)
• bits [12] = Schmitt trigger control (0=Disable, 1=Enable)
• bits [13] = Slew rate control (0=Slow, 1=Fast)

Parameters

drive_ability	Driving ability control (0=Low, 1=Middle, 2=High, 3=Ultral High)
schmitt_trig	Schmitt trigger control (0=Disable, 1=Enable)
slew_rate	Slew rate control (0=Slow, 1=Fast)

Returns

Encoded configuration value for DRCTL register

RZTN_GPIO_NONSAFETY

#define RZTN_GPIO_NONSAFETY   BIT(14)

Non safety region.

RZTN_GPIO_SAFETY

#define RZTN_GPIO_SAFETY   0U

Safety region.